11.7.2. Summary and description of the AHB-AP registers

Table 11.28 lists the AHB-AP registers.

Table 11.28. AHB-AP register summary

NameTypeAddress

Reset value

Description
Control and Status WordRead/write0x00See RegisterSee AHB-AP Control and Status Word Register
Transfer AddressRead/write0x040x00000000See AHB-AP Transfer Address Register
Data Read/writeRead/write0x0C- See AHB-AP Data Read/Write Register
Banked Data 0Read/write0x10 -See AHB-AP Banked Data Registers 0-3
Banked Data 1Read/write0x14 -See AHB-AP Banked Data Registers 0-3
Banked Data 2Read/write0x18-See AHB-AP Banked Data Registers 0-3
Banked Data 3Read/write0x1C-See AHB-AP Banked Data Registers 0-3
Debug ROM AddressRead only0xF80xE00FF003See AHB-AP Debug ROM Address Register
Identification RegisterRead only0xFC 0x14770011See AHB-AP ID Register

AHB-AP Control and Status Word Register

Use this register to configure and control transfers through the AHB interface.

Figure 11.19 shows the fields of the AHB-AP Control and Status Word Register.

Figure 11.19. AHB-AP Control and Status Word Register

Table 11.29 describes the fields of the AHB-AP Control and Status Word Register.

Table 11.29. AHB-AP Control and Status Word Register bit assignments

BitsFieldFunction
[31:30]-Reserved. Read as b010.
[29]MasterType[1]

0 = core.

1 = debug.

This bit cannot be cleared if COREACCEN = 0. Read back to confirm if accepted. It cannot be changed if transaction is outstanding. Debugger must first check TransinProg.

Reset value = 0b1.

[28:26]-Reserved, 0b000.
[25]Hprot1

User/Privilege control - HPROT[1].

Reset value = 0b1.

[24]-Reserved, 0b1.
[23:12]-Reserved, 0x000.
[11:8]Mode

Mode of operation bits:

b0000 = normal download/upload mode

b0001-b1111 are reserved.

Reset value = 0b0000.

[7]TransINProgTransfer in progress. This field indicates if a transfer is in progress on the APB master port.
[6] DbgStatus

Indicates the status of the DBGEN port. If DbgStatus is LOW, no AHB transfers carried out.

1 = AHB transfers permitted.

0 = AHB transfers not permitted.

[5:4]AddrInc

Auto address increment and pack mode on Read or Write data access. Only increments if the current transaction completes with no error.

Auto address incrementing and packed transfers are not performed on access to Banked Data registers 0x10 - 0x1C. The status of these bits is ignored in these cases.

Increments and wraps within a 4-KB address boundary, for example for word incrementing from 0x1000 to 0x1FFC. If the start is at 0x14A0, then the counter increments to 0x1FFC, wraps to 0x1000, then continues incrementing to 0x149C.

0b00 = auto increment off.

0b01 = increment single. Single transfer from corresponding byte lane.

0b10 = increment packed.

0b11 = reserved. No transfer.

Size of address increment is defined by the Size field [2:0].

Reset value: 0b00.

[3]-Reserved.
[2:0]SIZE

Size of access field:

b000 = 8 bits

b001 = 16 bits

b010 = 32 bits

b011-111 are reserved.

Reset value: b000.

[1] When clear, this bit prevents the debugger from setting the C_DEBUGEN bit in the Debug Halting Control and Status Register, and so prevent the debugger from being able to halt the core.

AHB-AP Transfer Address Register

Use this register to program the address of the current transfer.

Table 11.30 describes the fields of the AHB-AP Transfer Address Register.

Table 11.30. AHB-AP Transfer Address Register bit assignments

BitsFieldFunction
[31:0] ADDRESS

Current transfer address.

Reset value = 0x00000000.

AHB-AP Data Read/Write Register

Use this register to read and write data for the current transfer.

Table 11.31 describes the fields of the AHB-AP Data Read/Write Register.

Table 11.31. AHB-AP Data Read/Write Register bit assignments

BitsFieldFunction
[31:0]DATA

Write mode: data value to write for the current transfer

Read mode: data value to read for the current transfer

Reset value = 0x00000000

AHB-AP Banked Data Registers 0-3

Use these registers to directly map AHB-AP accesses to AHB transfers without rewriting the AHB-AP Transfer Address Register (TAR).

Table 11.32 describes the field of the AHB-AP Banked Data Registers.

Table 11.32. AHB-AP Banked Data Register bit assignments

BitsFieldFunction
[31:0]DATA

BD0-BD3 provide a mechanism for directly mapping through DAP accesses to AHB transfers without having to rewrite the TAR within a four location boundary, so for example BD0 reads/write from TAR, BD1 from TAR+4.

If DAPADDR[7:4] == 0x0001, so accessing AHB-AP registers in the range 0x10-0x1C, then the derived HADDR[31:0] is as follows:

Read mode: Data value read from the current transfer from external address TAR[31:4] + DAPADDR[3:0]. Auto address incrementing is not performed on DAP accesses to BD0-BD3.

Write mode: data value to write for the current transfer to external address TAR[31:4] + DAPADDR[3:0].

Banked transfers are only supported for word transfers. Non-word banked transfer size is currently ignored, assumed word access.

Reset value - 0x00000000.

AHB-AP Debug ROM Address Register

This register specifies the base address of the debug interface. It is read-only.

Table 11.33 describes the fields of the AHB-AP Debug ROM Address Register.

Table 11.33. AHB-AP Debug ROM Address Register bit assignments

BitsFieldFunction
[31:0]Debug ROM addressBase address of debug interface.

AHB-AP ID Register

This register defines the external interface on the access port.

Figure 11.20 shows the fields of the AHB-AP ID Register.

Figure 11.20. AHB-AP ID Register

Table 11.34 describes the fields of the AHB-AP ID Register.

Table 11.34. AHB-AP ID Register bit assignments

BitsFieldFunction
[31:28]RevisionThis field is zero for the first implementation of an AP design, and is updated for each major revision of the design.
[27:24]JEP-106 continuation codeFor an ARM-designed AP, this field has value 0b0100, 0x4.
[23:17]JEP-106 identity codeFor an ARM-designed AP, this field has value 0b0111011, 0x3B.
[16]Class0b1: This AP is a Memory Access Port
[15:8]-Reserved. SBZ.
[7:4]AP Variant0x1: Cortex-M3 variant
[3:0]AP Type0x1: AMBA AHB bus
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