11.4. FPB

The FPB:

The FPB unit contains:

The FPB contains a global enable, but also individual enables for the eight comparators. If the comparison for an entry matches, the address is remapped to the address set in the remap register plus an offset corresponding to the comparator that matched, or is remapped to a BKPT instruction if that feature is enabled. The comparison happens on the fly, but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking place from the Code space. The processor ignores this transaction however, and only the remapped transaction is used.

If an MPU is present, the MPU lookups are performed for the original address, not the remapped address.


  • Unaligned literal accesses are not remapped. The original access to the DCode bus takes place in this case.

  • Load exclusives are Unpredictable to the FPB. The address is remapped but the access does not take place as an exclusive load.

  • Remapping to the bit-band alias directly accesses the alias address, and does not remap to the bit-band region.

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