14.13. AHB timing characteristics

The processor does not contain memories within the macrocell. To achieve high system performance, and to give the implementor complete flexibility in their memory architecture, memory requests from the processor are presented directly to the AHB interfaces unregistered.

Because of this, the Cortex-M3 AHB outputs are valid approximately 50% into the cycle, and the AHB inputs have a setup requirement of approximately 50% of the clock period.

Table 14.4 describes the timing characteristics of each of the interfaces.

Table 14.4. Interface timing characteristics

interfaceTiming characteristics
ICODEInstruction address and control signals are generated from the ALU, and as a result are valid approximately 50% into the clock cycle. Read data (HRDATAI) and read response (HRESPI) are presented directly to the processor and have approximately 50% of clock period setup.
DCODECore data and debug requests are presented over this bus. Both data and debug requests are presented relatively early in the cycle, and they are generated from registers with a small amount of combinatorial logic after the register. Requests on this bus have more slack than those presented on the ICODE bus. Write data (HWDATAD) is presented directly from the ALU and is valid approximately 50% into the clock cycle. Read data (HRDATAD) and read response (HRESPD) are presented directly to the processor and have approximately 50% of clock period setup.
SYSTEMInstruction fetches from this bus are pipelined, as described in Pipelined instruction fetches, and data and debug requests to this bus are presented early in the cycle, so requests on this bus have more slack than those presented on the ICODE bus. Write data (HWDATAS) is presented directly from the ALU and is valid approximately 50% into the clock cycle. Read data (HRDATAS) and read response (HRESPS) are presented directly to the processor and have approximately 50% of clock period setup.
PPBData and debug requests to this bus are presented early in the cycle, so requests on this bus have more slack than those presented on the ICODE bus. Write data (PWDATA) is presented directly from the ALU and is valid approximately 50% into the clock cycle. Read data (PRDATA) is presented directly to the processor and has approximately 50% of clock period setup
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