A.11. ETM interface

Table A.11 lists the signals of the ETM interface.

Table A.11. ETM interface

ETMTRIGGER[3:0]OutputTrigger from DWT. One bit for each of the four DWT comparators.
ETMTRIGINOTD[3:0]OutputIndicates if the ETM is triggered on an instruction or data match.
ETMIVALIDOutputInstruction valid.
ETMIA[31:1]OutputPC of the instruction being executed.
ETMICCFAILOutputCondition Code fail. Indicates if the current instruction has failed or passed its conditional execution check.
ETMIBRANCHOutputOpcode is a branch target.
ETMIINDBROutputOpcode is an indirect branch target.

Interrupt status. Marks interrupt status of current cycle.

000 - no status

001 - interrupt entry

010 - interrupt exit

011 - interrupt return

100 - vector fetch and stack push.

ETMINTSTAT entry/return is asserted in the first cycle of the new interrupt context. Exit occurs without ETMIVALID.

ETMINTNUM[8:0]OutputMarks the interrupt number of the current execution context.
ETMISTALLOutputIndicates that the last instruction signalled by the core has not yet entered execute.
ETMFLUSHOutputA PC modifying opcode has executed, or an interrupt push/pop has started.
ETMPWRUPInputETM is enabled
ETMDVALIDOutputData valid
ETMCANCEL OutputInstruction cancelled
ETMFINDBROutputFlush is indirect. Marks flush hint destination cannot be inferred from the PC.
ETMFOLDOutputOpcode fold. An IT opcode has been folded in this cycle. PC advances past the current (16-bit) opcode plus the IT instruction (16 bits). This is reflected in the ETMIA.
ETMFIFOFULLInputDriven by the ETM (if connected). ETMFIFOFULL is asserted when the ETM FIFO is full, and causes the processor to stall until the FIFO has drained, so ensuring that no trace is lost.
DSYNCOutputSynchronization pulse from DWT.
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