13.2.2. Description of the TPIU registers

This section describes the TPIU registers.

Supported Sync Port Sizes Register

This register is read/write. Each bit location represents a single port size that is supported on the device, that is, 4, 2 or 1 in bit locations [3:0]. If the bit is set then that port size is permitted. By default the RTL is designed to support all port sizes, set to 0x0000000B. This register is constrained by the input tie-off MAXPORTSIZE. The external tie-off, MAXPORTSIZE, must be set during finalization of the ASIC to reflect the actual number of TRACEDATA signals wired to physical pins. This is to ensure that tools do not attempt to select a port width that an attached TPA cannot capture. The value on MAXPORTSIZE causes bits within the Supported Port Size register that represent wider widths to be clear, that is, unsupported.

Figure 13.3 shows the bit assignments.

Figure 13.3. Supported Sync Port Size Register bit assignments

Current Sync Port Size Register

This register is read/write. The Current Sync Port Size Register has the same format as the Supported Sync Port Sizes Register but only one bit is set, and all others must be zero. Writing values with more than one bit set, or setting a bit that is not indicated as supported is not supported and causes Unpredictable behavior.

It is more convenient to use the same format as the Supported Sync Port Sizes Register because it saves on having to decode the sizes later on in the device, and also maintains the format from the other register bank for checking for valid assignments.

On reset this defaults to the smallest possible port size, 1 bit, and so reads as 0x00000001.

Async Clock Prescaler Register

Use the Async Clock Prescaler Register to scale the baud rate of the asynchronous output.

Figure 13.4 shows the fields of the Async Clock Prescaler Register.

Figure 13.4. Async Clock Prescaler Register bit assignments

Table 13.5 describes the fields of the Async Clock Prescaler Register.

Table 13.5. Async Clock Prescaler Register bit assignments

BitsFieldFunction
[31:13]-Reserved. RAZ/SBZP.
[12:0]PRESCALERDivisor for TRACECLKIN is Prescaler + 1.

Selected Pin Protocol Register

Use the Selected Pin Protocol Register to select which protocol to use for trace output.

The register address, access type, and Reset state are:

Address

0xE00400F0

Access

Read/write

Reset state

0x01

Figure 13.5 shows the fields of the Selected Pin Protocol Register.

Figure 13.5. Selected Pin Protocol Register bit assignments

Table 13.6 describes the fields of the Selected Pin Protocol Register.

Table 13.6. Selected Pin Protocol Register bit assignments

BitsFieldFunction
[31:2]-Reserved
[1:0]PROTOCOL

00 - TracePort mode

01 - SerialWire Output (Manchester). This is the reset value. 10 - SerialWire Output (NRZ)

11 - Reserved.

Note

If this register is changed while trace data is being output, data corruption occurs.

Trigger control registers

This TPIU does not support trigger delay. To indicate this, the trigger control registers read zero.

EXTCTL port registers

This TPIU does not support EXTCTL ports. To indicate this, the EXTCTL port registers read zero.

Test pattern registers

This TPIU has no built in test pattern generator. To indicate this, the test pattern generator registers read zero.

Formatter and Flush Status Register

Use the Formatter and Flush Status Register to read the status of TPIU formatter.

The register address, access type, and Reset state are:

Address

0xE0040300

Access

Read only

Reset state

0x08

Figure 13.6 shows the fields of the Formatter and Flush Status Register.

Figure 13.6. Formatter and Flush Status Register bit assignments

Table 13.7 describes the fields of the Formatter and Flush Status Register.

Table 13.7. Formatter and Flush Status Register bit assignments

BitsFieldFunction
[31:4]-Reserved
[3]FtNonStopFormatter cannot be stopped
[2]TCPresentThis bit always reads zero
[1]FtStoppedThis bit always reads zero
[0]FlInProgThis bit always reads zero

Formatter and Flush Control Register

The Formatter and Flush Control Register.

The register address, access type, and Reset state are:

Address

0xE0040304

Access

Read/write

Reset state

0x102

Figure 13.7 shows the fields of the Formatter and Flush Control Register.

Figure 13.7.  Formatter and Flush Control Register bit assignments

Table 13.8 describes the fields of the Formatter and Flush Control Register.

Table 13.8. Formatter and Flush Control Register bit assignments

BitsFieldFunction
[31:14]-Reserved.
[13]StopTrigStop the formatter after a Trigger Event is observed.
[12]StopFIStop the formatter after a flush completes.
[11]-Reserved.
[10]TrigFIIndicates a trigger on Flush completion.
[9]TrigEVTIndicate a trigger on a Trigger Event.
[8]TrigINIndicate a trigger on TRIGIN being asserted.
[7]-Reserved.
[6]FOnManManually generate a flush of the system.
[5]FOnTrigGenerate flush using Trigger event.
[4]FOnFllnGenerate flush using the FLUSHIN interface.
[3:2]-Reserved.
[1]EnFContContinuous Formatting, no TRACECTL. This bit is set on reset.
[0]EnFTCEnable Formatting. Because TRACECTL is never present, this bit reads as zero.

Bit [8] of this register is always set to indicate that triggers are indicated when TRIGGER is asserted.

When one of the two single wire output modes is selected, bit [1] of this register enables the formatter to be bypassed. If the formatter is bypassed, only the ITM/DWT trace source (ATDATA2) passes through. The TPIU accepts and discards data that is presented on the ETM port (ATDATA1). This function is intended to be used when it is necessary to connect a device containing an ETM to a trace capture device that is only able to capture Serial Wire Output data. Enabling or disabling the formatter causes momentary data corruption.

Note

If the selected pin protocol register is set to 0x00 (TracePort mode), the Formatter and Flush Control Register always reads 0x102, because the formatter is automatically enabled. If one of the serial wire modes is then selected, the register reverts to its previously programmed value.

Formatter Synchronization Counter Register

The global synchronization trigger is generated by the Program Counter (PC) Sampler block. This means that there is no synchronization counter in the TPIU.

The register address, access type, and Reset state are:

Address

0xE0040308

Access

Read only

Reset state

0x00

Integration Test Registers

Use the Integration Test Registers to perform topology detection of the TPIU with other devices in a Cortex-M3 system. These registers enable direct control of outputs and the ability to read the value of inputs. The processor provides two Integration Test Registers:

  • Integration Test Register - ITATBCTR2

  • Integration Test Register - ITATBCTR0.

Integration Test Register-ITATBCTR2

The register address, access type, and Reset state are:

Address

0xE0040EF0

Access

Read only

Reset state

0x0

Figure 13.8 shows the fields of the Integration Test Register bit assignments.

Figure 13.8. Integration Test Register-ITATBCTR2 bit assignments

Table 13.9 describes the fields of the Integration Test Register bit assignments.

Table 13.9. Integration Test Register-ITATBCTR2 bit assignments

BitsFieldFunction
[31:1]-Reserved.
[0]ATREADY1This bit reads or sets the value of ATREADYS1 and ATREADYS2.
Integration Test Register-ITATBCTR0

The register address, access type, and Reset state are:

Address

0xE0040EF8

Access

Read only

Reset state

0x0

Figure 13.9 shows the fields of the Integration Test Register bit assignments.

Figure 13.9. Integration Test Register-ITATBCTR0 bit assignments

Table 13.10 describes the fields of the Integration Test Register bit assignments.

Table 13.10. Integration Test Register-ITATBCTR0 bit assignments

BitsFieldFunction
[31:1]-Reserved
[0]ATVALID1, ATVALID2This bit reads or sets the value of ATVALIDS1 OR-ed with ATVALIDS2.
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