14.2. AMBA 3 compliance

The processor matches the AMBA 3 specification except for maintaining control information during waited transfers. AMBA 3 AHB-Lite Protocol states that when the slave is requesting wait states the master must not change the transfer type, except for the following cases:

The processor does not match the above definition as it may change the access type from SEQ or NONSEQ to IDLE during a waited transfer. In effect this cancels the outstanding transfer which has not yet occurred due to the previous access being wait-stated and awaiting completion. This allows the processor to have a lower interrupt latency and higher performance in wait-stated systems.


Logic can be implemented external to Cortex-M3 if necessary to achieve total compliance, but this is only needed if peripherals require the control information to be maintained through a waited transfer. One way of implementing this is to mask the control information, such as HTRANS, whilst HREADY is low.

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