A.7. System bus interface

Table A.7 lists the signals of the system bus interface.

Table A.7. System bus interface

HADDRS[31:0]Output32-bit address.
HTRANSS[1:0]OutputIndicates the type of the current transfer. Can be IDLE, NONSEQUENTIAL, OR SEQUENTIAL.
HSIZES[2:0]OutputIndicates the size of the access. Can be 8, 16, or 32 bits.
HBURSTS[2:0]OutputIndicates if the transfer is part of a burst.
HPROTS[3:0]OutputProvides information on the access.
HWDATAS[31:0]Output32-bit write data bus.
HWRITESOutputWrite not read.
HMASTLOCKSOutputIndicates a transaction that must be atomic on the bus. This is only for bit-band writes (performed as read-modify-write).
EXREQSOutputExclusive request.
MEMATTRS[1:0]OutputMemory attributes. Bit 0 = Allocate, Bit 1 = shareable.

Indicates the current system bus master:

  • 0 = Core data side accesses or DAP access with master type set to 0.

  • 1 = DAP accesses with master type set to 1.

  • 2 = Core instruction side accesses. These include vector fetches that are marked as data by HPROTS[0].

  • 3 = Reserved. This value cannot appear on HMASTERS.

HRDATAS[31:0]InputRead data bus.
HREADYSInputWhen HIGH indicates that a transfer has completed on the bus. The signal is driven LOW to extend a transfer.
HRESPS[1:0]InputThe transfer response status. OKAY or ERROR.
EXRESPSInputExclusive response.
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