14.12. Memory attributes

The processor exports memory attributes on the System bus by the addition of a sideband bus, MEMATTR.

Table 14.3 shows the relationship between MEMATTR[0] and HPROT[3:2].

Table 14.3. Memory attributes

MEMATTR[0]HPROT[3]HPROT[2]Description
000Strongly ordered
001Device
010L1 cacheable, L2 not cacheable
100Invalid
101Invalid
110Cache WT, allocate on read
011Cache WB, allocate on read and write
111Cache WB, allocate on read
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