6.2. Resets

The processor has three reset inputs. Table 6.3 describes the reset inputs.

Table 6.3. Reset inputs

Reset inputDescription
PORESETnResets the entire processor system with the exception of SWJ-DP
SYSRESETn

Resets the entire processor system with the exception of debug logic in the:

  • Nested Vectored Interrupt Controller (NVIC)

  • Flash Patch and Breakpoint (FPB)

  • Data Watchpoint and Trace (DWT)

  • Instrumentation Trace Macrocell (ITM)

  • AHB-AP.

nTRSTSWJ-DP reset

Note

nTRST resets SWJ-DP. If your implementation does not contain SWJ-DP, this reset must be tied off.

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