6.1. Clocking

The processor has three functional clock inputs. Table 6.1 describes the processor clocks.

Table 6.1. Cortex-M3 processor clocks

ClockDomainDescription
FCLKProcessorFree running processor clock, used for sampling interrupts and clocking debug blocks. FCLK ensures that interrupts can be sampled, and sleep events can be traced, while the processor is sleeping.
HCLKProcessorProcessor clock.
DAPCLKProcessorDebug port Advanced High-performance Bus Access Port (AHB-AP) clock.

FCLK and HCLK are synchronous to each other. FCLK is a free running version of HCLK. For more information, see Chapter 7 Power Management. FCLK and HCLK must be balanced with respect to each other, with equal latencies into the processor.

The processor is integrated with components for debug and trace. Your macrocell might contain some, or all, of the clocks shown in Table 6-2.

Table 6.2. Cortex-M3 macrocell clocks

ClockDomainDescription
TRACECLKINTPIUClocks the output of the TPIU
DBGCLKSW-DPDebug clock
SWCLKTCK SWJ-DPDebug clock

SWCLKTCK is the clock for the debug interface domain of the SWJ-DP. In JTAG mode this is equivalent to TCK. In Serial Wire Mode this is the Serial Wire clock. It is asynchronous to all other clocks. DBGCLK is the clock for the debug interface domain of SW-DP. It is asynchronous to the other clocks.

TRACECLKIN is the reference clock for the Trace Port Interface Unit (TPIU). It is asynchronous to the other clocks.

Note

SWCLKTCK, DBGCLK, and TRACECLKIN only require to be driven if your implementation contains Serial Wire JTAG Debug Port (SWJ-DP), Serial Wire Debug Port (SW-DP), and TPIU blocks respectively. Otherwise, the clock inputs must be tied off.

Note

The processor also contains a STCLK input. This port is not a clock. It is a reference input for the SysTick counter, and it must be less than half the frequency of FCLK. STCLK is synchronized internally by the processor to FCLK.

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