9.2.2. Description of the MPU registers

This section contains a description of the MPU registers.

MPU Type Register

Use the MPU Type Register to see how many regions the MPU supports. Read bits [15:8] to determine if an MPU is present.

The register address, access type, and Reset state are:

Address

0xE000ED90

Access

Read-only

Reset state

0x00000800

Figure 9.1 shows the fields of the MPU Type Register.

Figure 9.1. MPU Type Register bit assignments

Table 9.2 describes the fields of the MPU Type Register.

Table 9.2. MPU Type Register bit assignments

BitsFieldFunction
[31:24]-Reserved.
[23:16]IREGIONBecause the processor core uses only a unified MPU, IREGION always contains 0x00.
[15:8]DREGIONNumber of supported MPU regions field. DREGION contains 0x08 if the implementation contains an MPU indicating eight MPU regions, otherwise it contains 0x00.
[7:0]- Reserved.
[0]SEPARATEBecause the processor core uses only a unified MPU, SEPARATE is always 0.

MPU Control Register

Use the MPU Control Register to:

  • enable the MPU

  • enable the default memory map (background region)

  • enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers.

When the MPU is enabled, at least one region of the memory map must be enabled for the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set and no regions are enabled, then only privileged code can operate.

When the MPU is disabled, the default address map is used, as if no MPU is present.

When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled.

Unless HFNMIENA is set, the MPU is not enabled when the exception priority is –1 or –2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK is enabled. The HFNMIENA bit enables the MPU when operating with these two priorities.

The register address, access type, and Reset state are:

Address

0xE000ED94

Access

Read/write

Reset state

0x00000000

Figure 9.2 shows the fields of the MPU Control Register.

Figure 9.2. MPU Control Register bit assignments

Table 9.3 describes the fields of the MPU Control Register.

Table 9.3. MPU Control Register bit assignments

BitsFieldFunction
[31:2]- Reserved.
[2]PRIVDEFENA

This bit enables the default memory map for privileged access, as a background region, when the MPU is enabled. The background region acts as if it was region number 1 before any settable regions. Any region that is set up overlays this default map, and overrides it.

If this bit = 0, the default memory map is disabled, and memory not covered by a region faults.

When the MPU is enabled and PRIVDEFENA is enabled, the default memory map is as described in Chapter 4 Memory Map. This applies to memory type, Execute Never (XN), cache and shareable rules. However, this only applies to privileged mode (fetch and data access). User mode code faults unless a region has been set up for its code and data.

When the MPU is disabled, the default map acts on both privileged and user mode code.

XN and SO rules always apply to the System partition whether this enable is set or not.

If the MPU is disabled, this bit is ignored.

Reset clears the PRIVDEFENA bit.

[1]HFNMIENA

This bit enables the MPU when in Hard Fault, NMI, and FAULTMASK escalated handlers. If this bit = 1 and the ENABLE bit = 1, the MPU is enabled when in these handlers. If this bit = 0, the MPU is disabled when in these handlers, regardless of the value of ENABLE. If this bit =1 and ENABLE = 0, behavior is Unpredictable.

Reset clears the HFNMIENA bit.

[0]ENABLE

MPU enable bit:

1 = enable MPU

0 = disable MPU.

Reset clears the ENABLE bit.

MPU Region Number Register

Use the MPU Region Number Register to select which protection region is accessed. Then write to the MPU Region Base Address Register or the MPU Attributes and Size Register to configure the characteristics of the protection region.

The register address, access type, and Reset state are:

Address

0xE000ED98

Access

Read/write

Reset state

Unpredictable

Figure 9.3 shows the fields of the MPU Region Number Register.

Figure 9.3. MPU Region Number Register bit assignments

Table 9.4 describes the fields of the MPU Region Number Register.

Table 9.4. MPU Region Number Register bit assignments

BitsFieldFunction
[31:8]-Reserved.
[7:0]REGIONRegion select field. Selects the region to operate on when using the Region Attribute and Size Register and the Region Base Address Register. It must be written first except when the address VALID + REGION fields are written, which overwrites this.

MPU Region Base Address Register

Use the MPU Region Base Address Register to write the base address of a region. The Region Base Address Register also contains a REGION field that you can use to override the REGION field in the MPU Region Number Register, if the VALID bit is set.

The Region Base Address register sets the base for the region. It is aligned by the size. So, a 64-KB sized region must be aligned on a multiple of 64KB, for example, 0x00010000 or 0x00020000.

The region always reads back as the current MPU region number. VALID always reads back as 0. Writing with VALID = 1 and REGION = n changes the region number to n. This is a short-hand way to write the MPU Region Number Register.

This register is Unpredictable if accessed other than as a word.

The register address, access type, and Reset state are:

Address

0xE000ED9C

Access

Read/write

Reset state

Unpredictable

Figure 9.4 shows the fields of the MPU Region Base Address Register.

Figure 9.4. MPU Region Base Address Register bit assignments

Table 9.5 describes the fields of the MPU Region Base Address Register.

Table 9.5. MPU Region Base Address Register bit assignments

BitsFieldFunction
[31:N]ADDRRegion base address field. The value of N depends on the region size, so that the base address is aligned according to an even multiple of size. The power of 2 size specified by the SZENABLE field of the MPU Region Attribute and Size Register defines how many bits of base address are used.
[4]VALID

MPU Region Number valid bit:

1 = MPU Region Number Register is overwritten by bits 3:0 (the REGION value).

0 = MPU Region Number Register remains unchanged and is interpreted.

[3:0]REGIONMPU region override field.

MPU Region Attribute and Size Register

Use the MPU Region Attribute and Size Register to control the MPU access permissions. The register is made up of two part registers, each of halfword size. These can be accessed using the individual size, or they can both be simultaneously accessed using a word operation.

The sub-region disable bits are Unpredictable for region sizes of 32 bytes, 64 bytes, and 128 bytes.

The register address, access type, and Reset state are:

Address

0xE000EDA0

Access

Read/write

Reset state

Unpredictable

Figure 9.5 shows the fields of the MPU Region Attribute and Size Register.

Figure 9.5. MPU Region Attribute and Size Register bit assignments

Table 9.6 describes the fields of the MPU Region Attribute and Size Register. For more information, see MPU access permissions.

Table 9.6. MPU Region Attribute and Size Register bit assignments

BitsFieldFunction    
[31:29]-Reserved.    
[28]XN

Instruction access disable bit:

1 = disable instruction fetches

0 = enable instruction fetches.

     
[27]-Reserved.    
[26:24]APData access permission field:     
 ValuePrivileged permissionsUser permissions     
 

b000

b001

b010

b011

b100

b101

b110

b111

No access

Read/write

Read/write Read/write

Reserved

Read-only

Read-only

Read-only.

No access

No access

Read-only

Read/write

Reserved

No access

Read-only

Read-only.

    
[23:22]-Reserved.      
[21:19]TEXType extension field.     
[18]S

Shareable bit:

1 = shareable

0 = not shareable.

    
[17]C

Cacheable bit:

1 = cacheable

0 = not cacheable.

    
[16]B

Bufferable bit:

1 = bufferable

0 = not bufferable.

    
[15:8]SRDSub-Region Disable (SRD) field. Setting an SRD bit disables the corresponding sub-region. Regions are split into eight equal-sized sub-regions. Sub-regions are not supported for region sizes of 128 bytes and less. For more information, see Sub-Regions.
[7:6]-Reserved.
[5:1]SIZEMPU Protection Region Size Field. See Table 9.7.
[0]ENABLERegion enable bit.    

For information about access permission, see MPU access permissions.

Table 9.7. MPU protection region size field

RegionSize
b00000Reserved
b00001Reserved
b00010Reserved
b00011Reserved
b0010032B
b0010164B
b00110128B
b00111256B
b01000512B
b010011KB
b010102KB
b010114KB
b011008KB
b0110116KB
b0111032KB
b0111164KB
b10000128KB
b10001256KB
b10010512KB
b100111MB
b101002MB
b101014MB
b101108MB
b1011116MB
b1100032MB
b1100164MB
b11010128MB
b11011256MB
b11100512MB
b111011GB
b111102GB
b111114GB
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