5.8.1. Exception exit

When returning from an exception, the processor is either:

Table 5.5 describes the postamble sequence.

Table 5.5. Exception exit steps

Action Description
Pop eight registersPops PC, xPSR, r0, r1, r2, r3, r12 and LR from stack selected by EXC_RETURN and adjusts SP, if not pre-empted.
Load current active interrupt number[1] and reverse stack-alignment adjustmentLoads current active interrupt number from bits [8:0] of stacked IPSR word. The processor uses this to track which exception to return to and to clear the activation bit on return. When bits [8:0] are zero, the processor returns to Thread Mode.
Select SPIf returning to an exception, SP is SP_main. If returning to Thread Mode, SP can be SP_main or SP_process.

[1] Because of dynamic priority changes, the NVIC uses interrupt numbers instead of interrupt priorities to determine which ISR is current.

Figure 5.5 shows an example of exception exit timing.

Figure 5.5. Exception exit timing

ETMINSTAT indicates:


If a higher priority exception occurs during the stack pop, the processor abandons the stack pop, rewinds the stack pointer, and services the exception as a tail-chain case.

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