5.5.1. Stacking

When the processor invokes an exception, it automatically pushes the following eight registers to the SP in the following order:

The SP is decremented by eight words by the completion of the stack push. Figure 5.1 shows the contents of the stack after an exception pre-empts the current program flow.

Figure 5.1. Stack contents after a pre-emption


After returning from the ISR, the processor automatically pops the eight registers from the stack. Interrupt return is passed as a data field in the LR, so ISR functions can be normal C/C++ functions, and do not require a veneer.

Table 5.4 describes the steps that the processor takes before it enters an ISR.

Table 5.4. Exception entry steps

Action Restartable? Description
Push eight registers[1]No.Pushes xPSR, PC, r0, r1, r2, r3, r12, and LR on selected stack.
Read vector tableYes. Late-arriving exception can cause restart.Reads vector table from memory based on table base + (exception number  4). Read on the ICode bus can be done simultaneously with register pushes on the DCode bus.
Read SP from vector tableNo.On Reset only, updates SP to top of stack from vector table. Other exceptions do not modify SP except to select stack, push, and pop.
Update PCNo.Updates PC with vector table read location. Late-arriving exceptions cannot be processed until the first instruction starts to execute.
Load pipelineYes. Pre-emption reloads pipeline from new vector table read.Loads instructions from location pointed to by vector table. This is done in parallel with register push.
Update LRNo.LR is set to EXC_RETURN to exit from exception. EXC_RETURN is one of 16 values as defined in ARMv7-M Architecture Reference Manual.

[1] When tail-chaining, this step is skipped.

Figure 5.2 shows an example of exception entry timing.

Figure 5.2. Exception entry timing

The NVIC indicates to the processor core, in the cycle after INTISR[2] was received, that an interrupt has been received, and the processor initiates the stack push and vector fetch in the following cycle.

When the stack push has completed, the first instruction of the ISR enters the execute stage of the pipeline. In the cycle that the ISR enters execute:

Figure 5.2 shows that there is a 12-cycle latency from asserting the interrupt to the first instruction of the ISR executing.

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