14.8. Access alignment

The processor supports unaligned data accesses using the ARMv6 model. The DCode and System bus interfaces contain logic that converts unaligned accesses to aligned accesses.

The unaligned data accesses are described in Table 14.2. The table shows the unaligned access in the first column, with the remaining columns showing what the access is converted into. Depending on the size and alignment of the unaligned access, it is converted into two or three aligned accesses.

Table 14.2. Bus mapper unaligned accesses

Unaligned accessAligned access
 Cycle 1Cycle 2Cycle 3
SizeADDR[1:0]HSIZEHADDR[1:0]HSIZEHADDR[1:0]HSIZEHADDR[1:0]
Halfword00Halfword00----
Halfword01Byte01Byte10--
Halfword10Halfword10----
Halfword11Byte11Byte{(Addr+4)[31:2],2b00}--
Word00Word00----
Word01Byte01Halfword10Byte{(Addr+4)[31:2],2b00}
Word10Halfword10Halfword{(Addr+4)[31:2],2b00}--
Word11Byte11Halfword{(Addr+4)[31:2],2b00}Byte{(Addr+4)[31:2],2b10}

Note

Unaligned accesses that cross into the bit-band alias region are not treated as bit-band requests, and the access is not remapped to the bit-band region. Instead, they are treated as a halfword or byte access to the bit-band alias region.

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