5.10. Exception control transfer

The processor transfers control to an ISR following the rules shown in Table 5.9.

Table 5.9. Transferring to exception processing

Processor activity at assertion of exception

Transfer to exception processing
Non-memory instruction Takes exception on completion of cycle, before the next instruction.
Load/store singleCompletes or abandons depending on bus status. Takes exception on the next cycle, depending on the bus wait states.
Load/store multipleCompletes or abandons current register and sets continuation counter into EPSR. Takes exception on the next cycle, depending on bus permission and Interruptible-Continuable Instruction (ICI) rules. For more information on ICI rules, see the ARMv7-M Architecture Reference Manual.
Exception entryThis is a late-arriving exception. If it has higher priority than the exception being entered, then the processor cancels the exception entry actions and takes the late-arriving exception. Late arriving results in a decision change (vector table) at interrupt processing time. When you enter a new handler, that is the first ISR instruction, normal pre-emption rules apply, and it is no longer classed as a late-arrival.
Tail-chainingThis is a late-arriving exception. If it has higher priority than the one being tail-chained, the processor cancels the preamble and takes the late-arriving exception.
Exception postambleIf the new exception has higher priority than the stacked exception to which the processor is returning, the processor tail-chains the new exception.
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