5.6. Tail-chaining

Tail-chaining is back-to-back processing of exceptions without the overhead of state saving and restoration between interrupts. The processor skips the pop of eight registers and push of eight registers when exiting one ISR and entering another because this has no effect on the stack contents.

The processor tail-chains if a pending interrupt has higher priority than all stacked exceptions.

Figure 5.3 shows an example of tail-chaining. If a pending interrupt has higher priority than the highest-priority stacked exception, the stack push or pop is omitted, and the processor immediately fetches the vector for the pending interrupt. The ISR that is tail-chained into starts execution six cycles after exiting the previous ISR.

Figure 5.3. Tail-chaining timing

On return from the last ISR, INTISR[2] is of higher priority than any stacked ISR, or other pended interrupt, and so the processor tail-chains to the ISR corresponding to INTISR[2]. In the cycle that the ISR for INTISR[2] enters execute:

Figure 5.3 shows that there is a 6-cycle latency when returning from the last ISR to executing the new ISR.

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