A.3. Miscellaneous

Table A.3 lists the leftover signals.

Table A.3. Miscellaneous signals

LOCKUPOutputLOCKUP gives immediate indication of seriously errant kernel software. This is the result of the core being locked up due to an unrecoverable exception following the activation of the processor’s built in system state protection hardware. For more information about the ARMv7-M architectural lock up conditions see the ARMv7-M Architecture Reference Manual.
SLEEPDEEPOutputIndicates that the Cortex-M3 clock can be stopped.
SLEEPINGOutputIndicates that the Cortex-M3 clock can be stopped.
CURRPRI[7:0]OutputIndicates what priority interrupt (or base boost) is currently used. CURRPRI represents the pre-emption priority, and does not indicate the secondary priority.
HALTEDOutputIn halting debug mode. HALTED remains asserted while the core is in debug.
TXEVOutputEvent transmitted as a result of SEV instruction. This is a single cycle pulse.
TRCENAOutputTrace Enable. This signal reflects the setting of bit [24] of the Debug Exception and Monitor Control Register. This signal gate the clock to the TPIU and ETM blocks to reduce power consumption when trace is disabled.

Static endian select:

1 = big-endian

0 = little-endian

This signal is sampled at reset, and cannot be changed when reset is inactive.

EDBGRQInputExternal debug request.
PPBLOCK[5:0]InputReserved. Must be tied to 6’b000000.
STCLKInputSystem Tick Clock.
STCALIB[25:0]InputSystem Tick Calibration.
RXEVInputCauses a wakeup from a WFE instruction.
VECTADDR[9:0]InputReserved. Must be tied to 10'b0000000000.
VECTADDRENInputReserved. Must be tied to 1'b0.
DNOTITRANSInputStatic tie-off which forces the processor to not permit I-Code and D-Code AHB transactions to occur at the same time. This permits a simple bus multiplexer to be instantiated externally to the processor.
AUXFAULT[31:0]InputAuxiliary fault status information from the system.
IFLUSHInputReserved. Instruction flush, must be tied to 0.
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