4.1. About the memory map

Figure 4.1 shows the fixed memory map.

Figure 4.1. Processor memory map

Table 4.1 shows the processor interfaces that are addressed by the different memory map regions

Table 4.1. Memory interfaces

Memory Map Interface
CodeInstruction fetches are performed over the ICode bus. Data accesses are performed over the DCode bus.
SRAMInstruction fetches and data accesses are performed over the system bus.
SRAM_bitbandAlias region. Data accesses are aliases. Instruction accesses are not aliases.
PeripheralInstruction fetches and data accesses are performed over the system bus.
Periph_bitbandAlias region. Data accesses are aliases. Instruction accesses are not aliases.
External RAMInstruction fetches and data accesses are performed over the system bus.
External DeviceInstruction fetches and data accesses are performed over the system bus.
Private Peripheral Bus

Accesses to:

  • Instrumentation Trace Macrocell (ITM)

  • Nested Vectored Interrupt Controller (NVIC)

  • Flashpatch and Breakpoint (FPB)

  • Data Watchpoint and Trace (DWT)

  • Memory Protection Unit (MPU)

are performed to the processor internal Private Peripheral Bus (PPB).

Accesses to:

  • Trace Point Interface Unit (TPIU)

  • Embedded Trace Macrocell (ETM)

  • System areas of the PPB memory map

are performed over the external PPB interface.

This memory region is Execute Never (XN), and so instruction fetches are prohibited. An MPU, if present, cannot change this.

SystemSystem segment for vendor system peripherals. This memory region is XN, and so instruction fetches are prohibited. An MPU, if present, cannot change this.

Table 4.2 shows the permissions of the processor memory regions.

Table 4.2. Memory region permissions

NameRegionDevice typeXNCache
Code0x00000000-0x1FFFFFFFNormal-WT
SRAM0x20000000-0x3FFFFFFFNormal-WBWA
    SRAM_1M+0000000---
    SRAM_31M+0100000-- 
    SRAM_bitband+2000000Internal--
    SRAM+4000000---
Peripheral0x40000000-0x5FFFFFFFDeviceXN-
    Periph_1IM+0000000---
    Periph_31IM+0100000---
    Periph_bit band+2000000Internal--
    Peripheral+4000000---
External RAM0x60000000-0x7FFFFFFFNormal-WBWA
External RAM0x80000000-0x9FFFFFFFNormal-WT
External Device0xA0000000-0xBFFFFFFFDeviceXN-
External Device0xC0000000-0xDFFFFFFFDeviceXN-
    Private Peripheral     Bus+4000000SOXN-
    System+0100000-XN-

Note

Private Peripheral Bus and System space at 0xE0000000 - 0xFFFFFFFF are permanently XN. The MPU cannot change this.

For a description of the processor bus interfaces, see Chapter 14 Bus Interface.

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