1.4. Execution pipeline stages

The following stages make up the pipeline:

Figure 1.2 shows the pipeline stages of the processor, and the pipeline operations that take place at each stage.

Figure 1.2.  Cortex-M3 pipeline stages

The names of the pipeline stages and their functions are:


Instruction fetch where data is returned from the instruction memory.


Instruction decode, generation of LSU address using forwarded register ports, and immediate offset or LR register branch forwarding.


Instruction execute, single pipeline with multi-cycle stalls, LSU address/data pipelining to AHB interface, multiply/divide, and ALU with branch result.

The pipeline structure provides a pipelined 2-cycle memory access with no ALU usage penalty, address generation forwarding for pointer indirection.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E