1.7. Store buffers

The processor contains two store buffers:

The core store buffer optimizes the case of STR rx,[ry,#imm] which is common in compiled code. This means that the next opcode can overlap the store's data phase, reducing the opcode to a single cycle from the perspective of the pipeline.

The bus-matrix interconnect within the processor manages the unaligned behavior of the core and bit-banding. The bus-matrix store buffer is useful for resolving system wait-states and unaligned accesses that are split over multiple transactions.

Only transactions marked as bufferable use the store buffers. Stacking operations are inherently non-bufferable and therefore also do not use either of the buffers.

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