10.2.1. Debug Halting Control and Status Register

The purpose of the Debug Halting Control and Status Register (DHCSR) is to:

The DHCSR:

Note

The DHCSR is only reset from a system reset, including power on. Bit 16 of DHCSR is Unpredictable on reset.

Figure 10.1 shows the arrangement of bits in the register.

Figure 10.1. Debug Halting Control and Status Register format

Table 10.2 shows the bit functions of the Debug ID Register.

Table 10.2. Debug Halting Control and Status Register

Bits

TypeFieldFunction
[31:16]WriteDBGKEYDebug Key. 0xA05F must be written whenever this register is written. Reads back as status bits [25:16]. If not written as Key, the write operation is ignored and no bits are written into the register.
[31:26]--Reserved, RAZ.
[25]ReadS_RESET_STIndicates that the core has been reset, or is now being reset, since the last time this bit was read. This a sticky bit that clears on read. So, reading twice and getting 1 then 0 means it was reset in the past. Reading twice and getting 1 both times means that it is being reset now (held in reset still).
[24]ReadS_RETIRE_STIndicates that an instruction has completed since last read. This is a sticky bit that clears on read. This determines if the core is stalled on a load/store or fetch.
[23:20]--Reserved, RAZ.
[19]ReadS_LOCKUPReads as one if the core is running (not halted) and a lockup condition is present.
[18]ReadS_SLEEP

Indicates that the core is sleeping (WFI, WFE or SLEEP-ON-EXIT). Must use C_HALT to gain control or wait for interrupt to wake-up. For more information on SLEEP-ON-EXIT see Table 7.1.

[17]ReadS_HALTThe core is in debug state when S_HALT is set.
[16]ReadS_REGRDYRegister Read/Write on the Debug Core Register Selector register is available. Last transfer is complete.
[15:6]--Reserved.
[5]Read/writeC_SNAPSTALL

If the core is stalled on a load/store operation the stall ceases and the instruction is forced to complete. This enables Halting debug to gain control of the core. It can only be set if:

C_DEBUGEN = 1

C_HALT = 1

The core reads S_RETIRE_ST as 0. This indicates that no instruction has advanced. This prevents misuse.

The bus state is Unpredictable when this is used.

S_RETIRE can detect core stalls on load/store operations.

[4]--Reserved.
[3]Read/writeC_MASKINTSMask interrupts when stepping or running in halted debug. Does not affect NMI, which is not maskable. Must only be modified when the processor is halted (S_HALT == 1).
[2]Read/writeC_STEPSteps the core in halted debug. When C_DEBUGEN = 0, this bit has no effect. Must only be modified when the processor is halted (S_HALT == 1).
[1]Read/writeC_HALTHalts the core. This bit is set automatically when the core Halts. For example Breakpoint. This bit clears on core reset. This bit can only be written if C_DEBUGEN is 1, otherwise it is ignored. When setting this bit to 1, C_DEBUGEN must also be written to 1 in the same value (value[1:0] is 2’b11). The core can halt itself, but only if C_DEBUGEN is already 1 and only if it writes with b11).
[0]Read/writeC_DEBUGEN

Enables debug. This can only be written by AHB-AP and not by the core. It is ignored when written by the core, which cannot set or clear it.

The core must write a 1 to it when writing C_HALT to halt itself.

If not enabled for Halting mode, C_DEBUGEN = 1, all other fields are disabled.

This register is not reset on a system reset. It is reset by a power-on reset. However, the C_HALT bit always clears on a system reset.

To halt on a reset, the following bits must be enabled:

Note

Writes to this register in any size other than word are Unpredictable. It is acceptable to read in any size, and you can use it to avoid or intentionally change a sticky bit.

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