10.2.2.  Debug Core Register Selector Register

The purpose of the Debug Core Register Selector Register (DCRSR) is to select the processor register to transfer data to or from.

The DCRSR:

Figure 10.2 shows the arrangement of bits in the register.

Figure 10.2. Debug Core Register Selector Register format

Table 10.3 shows the bit functions of the Debug Core Selector Register.

Table 10.3. Debug Core Register Selector Register

BitsTypeFieldFunction
[31:17]--Reserved
[16]WriteREGWnR

Write = 1

Read = 0

[15:5]---
[4:0]WriteREGSEL

5b00000 = R0

5b00001 = R1

5b01111 = DebugReturnAddress()

5b10000 = xPSR/Flags, Execution Number, and state information

5b10001 = MSP (Main SP)

5b10010 = PSP (Process SP)

5b10011 = RAZ/WI

All unused values reserved

This write-only register generates a handshake to the core to transfer data to or from Debug Core Register Data Register and the selected register. Until this core transaction is complete, bit [16], S_REGRDY, of the DHCSR is 0.

Note

  • Writes to this register in any size but word are Unpredictable.

  • PSR registers are fully accessible this way, whereas some read as 0 when using MRS instructions.

  • All bits can be written, but some combinations cause a fault when execution is resumed.

  • IT might be written and behaves as though in an IT block.

  • ICI can be written, though invalid values or when not used on an LDM/STM causes a fault, as would on return from exception. Changing ICI from a value to 0 causes the underlying LDM/STM to start, not continue.

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