10.1. About core debug

Core debug is accessed through the core debug registers. Debug access to these registers is by means of the Advanced High-performance Bus (AHB-AP) port, see AHB-AP. The processor can access these registers directly over the internal Private Peripheral Bus (PPB).

Table 10.1 shows the core debug registers.

Table 10.1. Core debug registers

Address Type Reset Value Description
0xE000EDF0Read/Write0x00000000[1]Debug Halting Control and Status Register
0xE000EDF4Write-only-Debug Core Register Selector Register
0xE000EDF8Read/Write-Debug Core Register Data Register
0xE000EDFCRead/Write0x00000000[2]Debug Exception and Monitor Control Register.

[1] Bits 5, 3, 2, 1, 0 are reset by PORESETn. Bit [1] is also reset by SYSRESETn and writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.

[2] Bits 16,17,18,19 are also reset by SYSRESETn and writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.

Also used is the Debug Fault Status Register see Debug Fault Status Register for more information

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E
Non-Confidential