12.1. About the DP

The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses. An external DP component accesses this interface. The Cortex-M3 system supports two possible DP implementations:


The SWJ-DP is designed to permit pin sharing of JTAG-TDO and JTAG-TDI when they are not being used for JTAG debug access. When used together with a Cortex-M3 TPIU, there are different options for the connection of Serial Wire Output (SWO), see Serial wire output connection.

These two DP implementations provide different mechanisms for debug access to the processor. Your implementation must contain only one of these components.


Your implementation might contain an alternative implementor-specific DP instead of SW-DP or SWJ-DP. See your implementor for details.

For more detailed information on the DP components, see the CoreSight Components Technical Reference manual.

For more information on the AHB-AP, see AHB-AP.

The DP and AP together are referred to as the Debug Access Port (DAP).

For more detailed information on the debug interface, see the ARM Debug Interface v5, Architecture Specification.

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