4.3. ROM memory table

Table 4.3 describes the ROM memory.

Table 4.3.  ROM table

OffsetValueNameDescription
0x0000xFFF0F003NVICPoints to the NVIC at 0xE000E000.
0x0040xFFF02003DWTPoints to the Data Watchpoint and Trace block at 0xE0001000.
0x0080xFFF03003FPBPoints to the Flash Patch and Breakpoint block at 0xE0002000.
0x00C0xFFF01003ITMPoints to the Instrumentation Trace block at 0xE0000000.
0x0100xFFF41002 or 003 if presentTPIUPoints to the TPIU. Value has bit [0] set to 1 if TPIU is fitted. TPIU is at 0xE0040000.
0x0140xFFF42003ETMPoints to the ETM. Value has bit [0] set to 1 if ETM is fitted. ETM is at 0xE0041000.
0x0180EndMarks the end of the ROM table. If CoreSight components are added, they are added starting from this location and the End marker is moved to the next location after the additional components.
0xFCC0x1MEMTYPEBits [31:1] RAZ. Bit [0] is set when the system memory map is accessible using the DAP. Bit [0] is clear when only debug resources are accessible using the DAP.
0xFD00x0PID4-
0xFD40x0PID5-
0xFD80x0PID6-
0xFDC0x0PID7-
0xFE00x0PID0-
0xFE40x0PID1-
0xFE80x0PID2-
0xFEC0x0PID3-
0xFF00x0DCID0-
0xFF40x10CID1-
0xFF80x05CID2-
0xFFC0xB1CID3-
Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E
Non-Confidential