5.9. Resets

The NVIC is reset at the same time as the core and controls the release of reset into the core. As a result, the behavior of reset is predictable. Table 5.7 shows the reset behavior.

Table 5.7. Reset actions

NVIC resets, holds core in resetNVIC clears most of its registers. The processor is in Thread mode, priority is privileged, and the stack is set to Main.
NVIC releases core from resetNVIC releases core from reset.
Core sets stackCore reads the start SP, SP_main, from vector-table offset 0.
Core sets PC and LRCore reads the start PC from vector-table offset. LR is set to 0xFFFFFFFF.
Reset routine runsNVIC has interrupts disabled, and NMI and Hard Fault are not disabled.

For more information about resets, see Chapter 6 Clocking and Resets.

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