3.1.2. Core debug registers

Table 3.2 gives a summary of the core debug registers. For a detailed description of the core debug registers, see Chapter 10 Core Debug.

Table 3.2. Core debug registers

Name of registerTypeAddress Reset Value
Debug Halting Control and Status RegisterRead/Write0xE000EDF00x00000000[1]
Debug Core Register Selector RegisterWrite-only0xE000EDF4-
Debug Core Register Data RegisterRead/Write0xE000EDF8-
Debug Exception and Monitor Control Register.Read/Write0xE000EDFC0x00000000[2]

[1] Bits [5], [3], [2], [1], [0] are reset by PORESETn. Bit [1] is also reset by SYSRESETn and by writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.

[2] Bits [16], [17], [18], [19] are also reset by SYSRESETn and by writing a 1 to the VECTRESET bit of the Application Interrupt and Reset Control Register.

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