3.1.1. Nested Vectored Interrupt Controller registers

Table 3.1 gives a summary of the Nested Vectored Interrupt Controller (NVIC) registers. For a detailed description of the NVIC registers, see Chapter 8 Nested Vectored Interrupt Controller .

Table 3.1. NVIC registers

Name of registerTypeAddressReset value
Interrupt Control Type RegisterRead-only0xE000E004[1]
SysTick Control and Status RegisterRead/write0xE000E0100x00000000
SysTick Reload Value RegisterRead/write0xE000E014Unpredictable
SysTick Current Value RegisterRead/write clear0xE000E018Unpredictable
SysTick Calibration Value RegisterRead-only0xE000E01CSTCALIB
Irq 0 to 31 Set Enable RegisterRead/write0xE000E1000x00000000
....
....
....
Irq 224 to 239 Set Enable RegisterRead/write0xE000E11C0x00000000
Irq 0 to 31 Clear Enable RegisterRead/write0xE000E1800x00000000
....
....
....
Irq 224 to 239 Clear Enable RegisterRead/write0xE000E19C0x00000000
Irq 0 to 31 Set Pending RegisterRead/write0xE000E2000x00000000
....
....
....
Irq 224 to 239 Set Pending RegisterRead/write0xE000E21C0x00000000
Irq 0 to 31 Clear Pending RegisterRead/write0xE000E2800x00000000
....
....
....
Irq 224 to 239 Clear Pending RegisterRead/write0xE000E29C0x00000000
Irq 0 to 31 Active Bit RegisterRead-only0xE000E3000x00000000
....
....
....
Irq 224 to 239 Active Bit RegisterRead-only0xE000E31C0x00000000
Irq 0 to 31 Priority RegisterRead/write0xE000E4000x00000000
....
....
....
Irq 236 to 239 Priority RegisterRead/write0xE000E4F00x00000000
CPUID Base RegisterRead-only0xE000ED000x411FC231
Interrupt Control State RegisterRead/write or read-only0xE000ED040x00000000
Vector Table Offset RegisterRead/write0xE000ED080x00000000
Application Interrupt/Reset Control RegisterRead/write0xE000ED0C0x00000000
System Control RegisterRead/write0xE000ED100x00000000
Configuration Control RegisterRead/write0xE000ED140x00000000
System Handlers 4-7 Priority RegisterRead/write0xE000ED180x00000000
System Handlers 8-11 Priority RegisterRead/write0xE000ED1C0x00000000
System Handlers 12-15 Priority RegisterRead/write0xE000ED200x00000000
System Handler Control and State RegisterRead/write0xE000ED240x00000000
Configurable Fault Status RegistersRead/write0xE000ED280x00000000
Hard Fault Status RegisterRead/write0xE000ED2C0x00000000
Debug Fault Status RegisterRead/write0xE000ED300x00000000
Mem Manage Address RegisterRead/write0xE000ED34Unpredictable
Bus Fault Address RegisterRead/write0xE000ED38Unpredictable
Auxiliary Fault Status RegisterRead/write0xE000ED3C0x00000000
PFR0: Processor Feature register0Read-only0xE000ED400x00000030
PFR1: Processor Feature register1Read-only0xE000ED440x00000200
DFR0: Debug Feature register0Read-only0xE000ED480x00100000
AFR0: Auxiliary Feature register0Read-only0xE000ED4C0x00000000
MMFR0: Memory Model Feature register0Read-only0xE000ED500x00000030
MMFR1: Memory Model Feature register1Read-only0xE000ED540x00000000
MMFR2: Memory Model Feature register2Read-only0xE000ED580x00000000
MMFR3: Memory Model Feature register3Read-only0xE000ED5C0x00000000
ISAR0: ISA Feature register0Read-only0xE000ED600x01141110
ISAR1: ISA Feature register1Read-only0xE000ED640x02111000
ISAR2: ISA Feature register2Read-only0xE000ED680x21112231
ISAR3: ISA Feature register3Read-only0xE000ED6C0x01111110
ISAR4: ISA Feature register4Read-only0xE000ED700x01310102
Software Trigger Interrupt RegisterWrite Only0xE000EF00-
Peripheral identification register (PID4)Read-only0xE000EFD00x04
Peripheral identification register (PID5)Read-only0xE000EFD40x00
Peripheral identification register (PID6)Read-only0xE000EFD80x00
Peripheral identification register (PID7)Read-only0xE000EFDC0x00
Peripheral identification register Bits [7:0] (PID0)Read-only0xE000EFE00x00
Peripheral identification register Bits [15:8] (PID1)Read-only0xE000EFE40xB0
Peripheral identification register Bits [23:16] (PID2)Read-only0xE000EFE80x1B
Peripheral identification register Bits [31:24] (PID3)Read-only0xE000EFEC0x00
Component identification register Bits [7:0] (CID0)Read Only0xE000EFF00x0D
Component identification register Bits [15:8] (CID1)Read-only0xE000EFF40xE0
Component identification register Bits [23:16] (CID2)Read-only0xE000EFF80x05
Component identification register Bits [31:24] (CID3)Read-only0xE000EFFC0xB1

[1] Reset value depends on the number of interrupts defined.

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