1.2.2. Processor core

The processor core implements the ARMv7-M architecture. It has the following main features:

Registers

The processor contains:

  • 13 general purpose 32-bit registers

  • Link Register (LR)

  • Program Counter (PC)

  • Program Status Register, xPSR

  • two banked SP registers.

Memory interface

The processor has a Harvard interface to enable simultaneous instruction fetches with data load/stores. Memory accesses are controlled by:

  • A separate Load Store Unit (LSU) that decouples load and store operations from the Arithmetic and Logic Unit (ALU).

  • A 3-word entry Prefetch Unit (PFU). One word is fetched at a time. This can be two Thumb instructions, one word-aligned Thumb-2 instruction, or the upper/lower halfword of a halfword-aligned Thumb-2 instruction with one Thumb instruction, or the lower/upper halfword of another halfword-aligned Thumb-2 instruction. All fetch addresses from the core are word aligned. If a Thumb-2 instruction is halfword aligned, two fetches are necessary to fetch the Thumb-2 instruction. However, the 3-entry prefetch buffer ensures that a stall cycle is only necessary for the first halfword Thumb-2 instruction fetched.

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