2.6. Instruction set

The processor does not support ARM instructions.

The processor supports all ARMv6 Thumb instructions except those listed in Table 2.4.

Table 2.4. Nonsupported Thumb instructions

Instruction Action if executed
BLX(1)Branch with link and exchangeBLX(1) always faults.
SETENDSet endiannessSETEND always faults. A configuration pin selects Cortex-M3 endianness.

The processor supports the Thumb-2 instructions listed in Table 2.5.

Table 2.5. Supported Thumb-2 instructions

Instruction typeSizeInstructions
Data operations16ADC, ADD, AND, ASR, BIC, CMN, CMP, CPY, EOR, LSL, LSR, MOV, MUL, MVN, NEG, ORR, ROR, SBC, SUB, TST, REV, REVH, REVSH, SXTB, SXTH, UXTB, and UXTH.
Branches16B<cond>, B, BL, BX, and BLX. Note, no BLX with immediate.
Load-store single16LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH.
Load-store multiple16LDMIA, POP, PUSH, and STMIA.
Exception generating16BKPT stops in debug if debug enabled, fault if debug disabled. SVC faults to the SVCall handler.
Data operations with immediate32ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}.
Data operations with large immediate32

MOVW, MOVT, ADDW, and SUBW.

MOVW and MOVT have a 16-bit immediate. This means they can replace literal loads from memory.

ADDW and SUBW have a 12-bit immediate. This means they can replace many from memory literal loads.

Bit-field operations32BFI, BFC, UBFX, and SBFX. These are bitwise operations enabling control of position and size in bits. These both support C/C++ bit fields, in structs, in addition to many compare and some AND/OR assignment expressions.
Data operations with three registers32ADC{S}. ADD{S}, CMN, RSB{S}, SBC{S}, SUB{S}, CMP, AND{S}, TST, BIC{S}, EOR{S}, TEQ, ORR{S}, MOV{S}, ORN{S}, and MVN{S}. No PKxxx instructions.
Shift operations32ASR{S}, LSL{S}, LSR{S}, RRX {S}, and ROR {S}.
Miscellaneous32

REV, REVH, REVSH, RBIT, CLZ, SXTB, SXTH, UXTB, and UXTH.

Extension instructions same as corresponding v6 16-bit instructions.

Table branch32TBB and TBH table branches for switch/case use. These are LDR with shifts and then branch.
Multiply32MUL, MLA, and MLS.
Multiply with 64-bit result32UMULL, SMULL, UMLAL, and SMLAL.
Load-store addressing32

Supports Format PC+/-imm12, Rbase+imm12, Rbase+/-imm8, and adjusted register including shifts.

T variants used when in Privilege mode.

Load-store single32LDR, LDRB, LDRSB, LDRH, LDRSH, STR, STRB, STRH, and T variants. PLD and PLI are both hints and so act as a NOP.
Load-store multiple32STM, LDM, LDRD, and STRD.
Load-store exclusive32

LDREX, STREX, LDREXB, LDREXH, STREXB, STREXH, CLREX.

Fault if no local monitor. This is IMP DEF.

LDREXD and STREXD are not included in this profile.

Branches 32B, BL, and B<cond>. No BLX (1) because always changes state. No BXJ.
System32

MSR(2) and MRS(2) replace MSR/MRS but also do more. These access the other stacks and also the status registers.

CPSIE/CPSID 32-bit forms are not supported.

No RFE or SRS.

System16CPSIE and CPSID are quick versions of MSR(2) instructions and use the standard Thumb-2 encodings, but only permit use of i and f and not a.
Extended3232NOP (all forms), Coprocessor (MCR, MCR2, MCRR, MRC, MRC2, and MRRC), and YIELD (hinted NOP). Note, no MRS(1), MSR(1), or SUBS (PC return link).
Combined branch16CBZ and CBNZ (Compare and Branch if register is Zero or Non-Zero).
Extended16IT and NOP. This includes YIELD.
Divide32SDIV and UDIV. 32/32 divides both signed and unsigned with 32-bit quotient result, no remainder, it can be derived by subtraction. Early out is permitted.
Sleep16, 32WFI, WFE, and SEV are in the class of hinted NOP instructions that control sleep behavior.
Barriers32ISB, DSB, and DMB are barrier instructions that ensure certain actions have taken place before the next instruction is executed.
Saturation32

SSAT and USAT perform saturation on a register. They perform the following:

Normalize the value using shift test for overflow from a selected bit position, the Q value.

Set the xPSR Q bit if so, saturate the value if overflow detected.

Saturation refers to the largest unsigned value or the largest/smallest signed value for the size selected.

Note

All coprocessor instructions generate a NO CoProcessor (NOCP) fault.

Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E
Non-Confidential