8.2.2. NVIC register descriptions

The sections that follow describe how to use the NVIC registers.

Note

The Memory Protection Unit (MPU) registers, and the debug registers are described in Chapter 9 Memory Protection Unit and Chapter 10 Core Debug respectively.

Interrupt Controller Type Register

Read the Interrupt Controller Type Register to see the number of interrupt lines that the NVIC supports.

The register address, access type, and Reset state are:

Address

0xE000E004

Access

Read-only

Reset state

Depends on the number of interrupts defined in this processor implementation.

Figure 8.1 shows the fields of the Interrupt Controller Type Register.

Figure 8.1. Interrupt Controller Type Register bit assignments

Table 8.2 describes the fields of the Interrupt Controller Type Register.

Table 8.2. Interrupt Controller Type Register bit assignments

Bits Field Function
[31:5]-Reserved.
[4:0]INTLINESNUM

Total number of interrupt lines in groups of 32:

b00000 = 0...32[1]

b00001 = 33...64

b00010 = 65...96

b00011 = 97...128

b00100 = 129...160

b00101 = 161...192

b00110 = 193...224

b00111 = 225...256a

[1] The processor only supports between 1 and 240 external interrupts.

SysTick Control and Status Register

Use the SysTick Control and Status Register to enable the SysTick features.

The register address, access type, and Reset state are:

Address

0xE000E010

Access

Read/write

Reset state

0x00000000

Figure 8.2 shows the fields of the SysTick Control and Status Register.

Figure 8.2. SysTick Control and Status Register bit assignments

Table 8.3 describes the fields of the SysTick Control and Status register.

Table 8.3.  SysTick Control and Status Register bit assignments

BitsFieldFunction
[31:17]-Reserved.
[16]COUNTFLAGReturns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read.
[2]CLKSOURCE

0 = external reference clock.

1 = core clock.

If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable.

[1]TICKINT

1 = counting down to 0 pends the SysTick handler.

0 = counting down to 0 does not pend the SysTick handler. Software can use the COUNTFLAG to determine if ever counted to 0.

[0]ENABLE

1 = counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.

0 = counter disabled.

SysTick Reload Value Register

Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0.

Therefore, as a multi-shot timer, repeated over and over, it fires every N+1 clock pulse, where N is any value from 1 to 0x00FFFFFF. So, if the tick interrupt is required every 100 clock pulses, 99 must be written into the RELOAD. If a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. For example, if a tick is next required after 400 clock pulses, 400 must be written into the RELOAD.

The register address, access type, and Reset state are:

Address

0xE000E014

Access

Read/write

Reset state

Unpredictable

Figure 8.3 shows the fields of the SysTick Reload Value Register.

Figure 8.3. SysTick Reload Value Register bit assignments

Table 8.4 describes the fields of the SysTick Reload Value Register.

Table 8.4. SysTick Reload Value Register bit assignments

BitsFieldFunction
[31:24]-Reserved
[23:0]RELOADValue to load into the SysTick Current Value Register when the counter reaches 0.

SysTick Current Value Register

Use the SysTick Current Value Register to find the current value in the register.

The register address, access type, and Reset state are:

Address

0xE000E018

Access

Read/write clear

Reset state

Unpredictable

Figure 8.4 shows the fields of the SysTick Current Value Register.

Figure 8.4. SysTick Current Value Register bit assignments

Table 8.5 describes the fields of the SysTick Current Value Register.

Table 8.5. SysTick Current Value Register bit assignments

BitsFieldFunction
[31:24]-Reserved
[23:0]CURRENT

Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care.

This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.

SysTick Calibration Value Register

Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.

The register address, access type, and Reset state are:

Address

0xE000E01C

Access

Read

Reset state

STCALIB

Figure 8.5 describes the fields of the SysTick Calibration Value Register.

Figure 8.5. SysTick Calibration Value Register bit assignments

Table 8.6 describes the fields of the SysTick Calibration Value Register.

Table 8.6. SysTick Calibration Value Register bit assignments

BitsFieldFunction
[31]NOREF1 = the reference clock is not provided.
[30]SKEW1 = the calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock.
[29:24]-Reserved
[23:0]TENMSThis value is the Reload value to use for 10ms timing. Depending on the value of SKEW, this might be exactly 10ms or might be the closest value.If this reads as 0, then the calibration value is not known. This is probably because the reference clock is an unknown input from the system or scalable dynamically.

Interrupt Set-Enable Registers

Use the Interrupt Set-Enable Registers to:

  • enable interrupts

  • determine which interrupts are currently enabled.

Each bit in the register corresponds to one of 32 interrupts. Setting a bit in the Interrupt Set-Enable Register enables the corresponding interrupt.

When the enable bit of a pending interrupt is set, the processor activates the interrupt based on its priority. When the enable bit is clear, asserting its interrupt signal pends the interrupt, but it is not possible to activate the interrupt, regardless of its priority. Therefore, a disabled interrupt can serve as a latched general-purpose I/O bit. You can read it and clear it without invoking an interrupt.

Clear an Interrupt Set-Enable Register bit by writing a 1 to the corresponding bit in the Interrupt Clear-Enable Register (see Interrupt Clear-Enable Registers).

Note

Clearing an Interrupt Set-Enable Register bit does not affect currently active interrupts. It only prevents new activations.

The register address, access type, and Reset state are:

Address

0xE000E100-0xE000E11C

Access

Read/write

Reset state

0x00000000

Table 8.7 describes the field of the Interrupt Set-Enable Register.

Table 8.7. Interrupt Set-Enable Register bit assignments

BitsFieldFunction
[31:0]SETENA

Interrupt set enable bits. For write operation:

1 = enable interrupt

0 = no effect.

For read operation:

1 = enable interrupt

0 = disable interrupt

Writing 0 to a SETENA bit has no effect. Reading the bit returns its current enable state. Reset clears the SETENA fields.

Interrupt Clear-Enable Registers

Use the Interrupt Clear-Enable Registers to:

  • disable interrupts

  • determine which interrupts are currently disabled.

Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Enable Register bit disables the corresponding interrupt.

The register address, access type, and Reset state are:

Address

0xE000E180-0xE000E19C

Access

Read/write

Reset state

0x00000000

Table 8.8 describes the field of the Interrupt Clear-Enable Register.

Table 8.8. Interrupt Clear-Enable Register bit assignments

BitsFieldFunction
[31:0]CLRENA

Interrupt clear-enable bits. For write operation:

1 = disable interrupt

0 = no effect.

For read operation:

1 = enable interrupt

0 = disable interrupt.

Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state.

Interrupt Set-Pending Register

Use the Interrupt Set-Pending Register to:

  • force interrupts into the pending state

  • determine which interrupts are currently pending.

Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Set-Pending Register bit pends the corresponding interrupt.

Clear an Interrupt Set-Pending Register bit by writing a 1 to the corresponding bit in the Interrupt Clear-Pending Register (see Interrupt Clear-Pending Register). Clearing the Interrupt Set-Pending Register bit puts the interrupt into the non-pended state.

Note

Writing to the Interrupt Set-Pending Register has no affect on an interrupt that is already pending or is disabled.

The register address, access type, and Reset state are:

Address

0xE000E200-0xE000E21C

Access

Read/write

Reset state

0x00000000

Table 8.9 describes the field of the Interrupt Set-Pending Register.

Table 8.9. Interrupt Set-Pending Register bit assignments

BitsFieldFunction
[31:0]SETPEND

Interrupt set-pending bits:

1 = pend the corresponding interrupt

0 = corresponding interrupt not pending.

Writing 0 to a SETPEND bit has no effect. Reading the bit returns its current state.

Interrupt Clear-Pending Register

Use the Interrupt Clear-Pending Register to:

  • clear pending interrupts

  • determine which interrupts are currently pending.

Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state.

Note

Writing to the Interrupt Clear-Pending Register has no effect on an interrupt that is active unless it is also pending.

The register address, access type, and Reset state are:

Address

0xE000E280-0xE000E29C

Access

Read/write

Reset state

0x00000000

Table 8.10 describes the field of the Interrupt Clear-Pending Registers.

Table 8.10. Interrupt Clear-Pending Registers bit assignments

BitsFieldFunction
[31:0]CLRPEND

Interrupt clear-pending bits:

1 = clear pending interrupt

0 = do not clear pending interrupt.

Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state.

Active Bit Register

Read the Active Bit Register to determine which interrupts are active. Each flag in the register corresponds to one of the 32 interrupts.

The register address, access type, and Reset state are:

Address

0xE000E300-0xE00031C

Access

Read-only

Reset state

0x00000000

Table 8.11 describes the field of the Active Bit Register.

Table 8.11. Active Bit Register bit assignments

BitsFieldFunction
[31:0]ACTIVE

Interrupt active flags:

1 = interrupt active or pre-empted and stacked

0 = interrupt not active or stacked.

Interrupt Priority Registers

Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest.

The priority registers are stored with the Most Significant Bit (MSB) first. This means that if there are four bits of priority, the priority value is stored in bits [7:4] of the byte. However, if there are three bits of priority, the priority value is stored in bits [7:5] of the byte. This means that an application can work even if it does not know how many priorities are possible.

The register address, access type, and Reset state are:

Address

0xE000E400-0xE000E41F

Access

Read/write

Reset state

0x00000000

Figure 8.6 shows the fields of Interrupt Priority Registers 0-7.

Figure 8.6. Interrupt Priority Registers 0-31 bit assignments

The lower PRI_n bits can specify subpriorities for priority grouping. See Exception priority.

Table 8.12 describes the fields of the Interrupt Priority Registers.

Table 8.12. Interrupt Priority Registers 0-31 bit assignments

BitsFieldFunction
[7:0]PRI_nPriority of interrupt n

CPU ID Base Register

Read the CPU ID Base Register to determine:

  • the ID number of the processor core

  • the version number of the processor core

  • the implementation details of the processor core.

The register address, access type, and Reset state are:

Address

0xE000ED00

Access

Read-only

Reset state

0x411FC231

Figure 8.7 shows the fields of the CPUID Base Register.

Figure 8.7. CPUID Base Register bit assignments

Table 8.13 describes the fields of the CPUID Base Register.

Table 8.13. CPUID Base Register bit assignments

BitsFieldFunction
[31:24]IMPLEMENTERImplementer code. ARM is 0x41
[23:20]VARIANTImplementation defined variant number.
[19:16]ConstantReads as 0xF
[15:4]PARTNO

Number of processor within family:

[11:10] b11 = Cortex family

[9:8] b00 = version

[7:6] b00 = reserved

[5:4] b10 = M (v7-M)

[3:0] X = family member. Cortex-M3 family is b0011.

[3:0]REVISIONImplementation defined revision number.

Interrupt Control State Register

Use the Interrupt Control State Register to:

  • set a pending Non-Maskable Interrupt (NMI)

  • set or clear a pending SVC

  • set or clear a pending SysTick

  • check for pending exceptions

  • check the vector number of the highest priority pended exception

  • check the vector number of the active exception.

The register address, access type, and Reset state are:

Address

0xE000ED04

Access

Read/write or read-only

Reset state

0x00000000

Figure 8.8 shows the fields of the Interrupt Control State Register.

Figure 8.8. Interrupt Control State Register bit assignments

Table 8.14 describes the fields of the Interrupt Control State Register.

Table 8.14. Interrupt Control State Register bit assignments

BitsFieldTypeFunction
[31]NMIPENDSETRead/write

Set pending NMI bit:

1 = set pending NMI

0 = do not set pending NMI.

NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers.

[30:29]--Reserved.
[28]PENDSVSETRead/write

Set pending pendSV bit:

1 = set pending pendSV

0 = do not set pending pendSV.

[27]PENDSVCLRWrite-only

Clear pending pendSV bit:

1 = clear pending pendSV

0 = do not clear pending pendSV.

[26]PENDSTSETRead/write

Set a pending SysTick bit

1 = set pending SysTick

0 = do not set pending SysTick.

[25]PENDSTCLRWrite-only

Clear pending SysTick bit:

1 = clear pending SysTick

0 = do not clear pending SysTick.

[24]--Reserved
[23]ISRPREEMPTRead-onlyYou must only use this at debug time. It indicates that a pending interrupt becomes active in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
[22]ISRPENDINGRead-only

Interrupt pending flag. Excludes NMI and Faults:

1 = interrupt pending

0 = interrupt not pending.

[21:12]VECTPENDINGRead-onlyPending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR.
[11]RETTOBASERead-onlyThis bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set.
[10]--Reserved.
[9]--Reserved
[8:0]VECTACTIVERead-only

Active ISR number field. VECTACTIVE contains the interrupt number of the currently running ISR, including NMI and Hard Fault. A shared handler can use VECTACTIVE to determine which interrupt invoked it. You can subtract 16 from the VECTACTIVE field to index into the Interrupt Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority Registers. INTISR[0] has vector number 16.

Reset clears the VECTACTIVE field.

Vector Table Offset Register

Use the Vector Table Offset Register to determine:

  • if the vector table is in RAM or code memory

  • the vector table offset.

The register address, access type, and Reset state are:

Address

0xE000ED08

Access

Read/write

Reset state

0x00000000

Figure 8.9 shows the fields of the Vector Table Offset Register.

Figure 8.9. Vector Table Offset Register bit assignments

Table 8.15 describes the fields of the Vector Table Offset Register.

Table 8.15. Vector Table Offset Register bit assignments

BitsFieldFunction
[31:30]-Reserved
[29]TBLBASETable base is in Code (0) or RAM (1)
[28:7]TBLOFFVector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space.
[6:0]-Reserved.

The Vector Table Offset Register positions the vector table in CODE or SRAM space. The default, on reset, is 0 (CODE space). When setting a position, the offset must be aligned based on the number of exceptions in the table. This means that the minimal alignment is 32 words that you can use for up to 16 interrupts. For more interrupts, you must adjust the alignment by rounding up to the next power of two. For example, if you require 21 interrupts, the alignment must be on a 64-word boundary because table size is 37 words, next power of two is 64.

Application Interrupt and Reset Control Register

Use the Application Interrupt and Reset Control Register to:

  • determine data endianness

  • clear all active state information for debug or to recover from a hard failure

  • execute a system reset

  • alter the priority grouping position (binary point).

The register address, access type, and Reset state are:

Address

0xE000ED0C

Access

Read/write

Reset state

0x00000000

Figure 8.10 shows the fields of the Application Interrupt and Reset Control Register.

Figure 8.10. Application Interrupt and Reset Control Register bit assignments

Table 8.16 describes the fields of the Application Interrupt and Reset Control Register.

Table 8.16. Application Interrupt and Reset Control Register bit assignments

BitsFieldFunction
[31:16]VECTKEYRegister key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored.
[31:16]VECTKEYSTATReads as 0xFA05.
[15]ENDIANESS

Data endianness bit:

1 = big endian

0 = little endian.

ENDIANESS is sampled from the BIGEND input port during reset. You cannot change ENDIANESS outside of reset.

[14:11]-Reserved
[10:8]PRIGROUPInterrupt priority grouping field:
  

PRIGROUP 0

1

2

3

4

5

6

7

Split of pre-emption priority from subpriority

7.1 indicates seven bits of pre-emption priority, one bit of subpriority

6.2 indicates six bits of pre-emption priority, two bits of subpriority

5.3 indicates five bits of pre-emption priority, three bits of subpriority

4.4 indicates four bits of pre-emption priority, four bits of subpriority

3.5 indicates three bits of pre-emption priority, five bits of subpriority

2.6 indicates two bits of pre-emption priority, six bits of subpriority

1.7 indicates one bit of pre-emption priority, seven bits of subpriority

0.8 indicates no pre-emption priority, eight bits of subpriority.

  

PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0.

The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices.

[7:3]- Reserved.
[2]SYSRESETREQCauses a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running.
[1]VECTCLRACTIVE

Clear active vector bit:

1 = clear all state information for active NMI, fault, and interrupts

0 = do not clear.

It is the responsibility of the application to reinitialize the stack.

The VECTCLRACTIVE bit is for returning to a known state during debug. The VECTCLRACTIVE bit self-clears.

IPSR is not cleared by this operation. So, if used by an application, it must only be used at the base level of activation, or within a system handler whose active bit can be set.

[0]VECTRESET

System Reset bit. Resets the system, with the exception of debug components:

1 = reset system

0 = do not reset system.

The VECTRESET bit self-clears. Reset clears the VECTRESET bit.

For debugging, only write this bit when the core is halted.

Note

SYSRESETREQ is cleared by a system reset, which means that asserting VECTRESET at the same time may cause SYSRESETREQ to be cleared in the same cycle as it is written to. This may prevent the external system from seeing SYSRESETREQ. It is therefore recommended that VECTRESET and SYSRESETREQ be used exclusively and never both written to 1 at the same time.

System Control Register

Use the System Control Register for power-management functions:

  • signal to the system when the processor can enter a low power state

  • control how the processor enters and exits low power states.

The register address, access type, and Reset state are:

Address

0xE000ED10

Access

Read/write

Reset state

0x00000000

Figure 8.11 shows the fields of the System Control Register.

Figure 8.11. System Control Register bit assignments

Table 8.17 describes the fields of the System Control Register.

Table 8.17. System Control Register bit assignments

BitsFieldFunction
[31:5]-Reserved.
[4]SEVONPENDWhen enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE.
[2]SLEEPDEEP

Sleep deep bit:

1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped.

0 = not OK to turn off system clock.

For more information about the use of SLEEPDEEP, see Chapter 7 Power Management.

[1]SLEEPONEXIT

Sleep on exit when returning from Handler mode to Thread mode:

1 = sleep on ISR exit.

0 = do not sleep when returning to Thread mode.

Enables interrupt driven applications to avoid returning to empty main application.

[0]-Reserved.

Configuration Control Register

Use the Configuration Control Register to:

  • enable NMI, Hard Fault and FAULTMASK to ignore bus fault

  • trap divide by zero, and unaligned accesses

  • enable user access to the Software Trigger Exception Register

  • control entry to Thread Mode.

The register address, access type, and Reset state are:

Address

0xE000ED14

Access

Read/write

Reset state

0x00000000

Figure 8.12 shows the fields of the Configuration Control Register.

Figure 8.12. Configuration Control Register bit assignments

Table 8.18 describes the fields of the Configuration Control Register.

Table 8.18. Configuration Control Register bit assignments

BitsFieldFunction
[9]STKALIGN

1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return.

0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry.

[8]BFHFNMIGNWhen enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored – you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them.
[4]DIV_0_TRPTrap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register.
[3]UNALIGN_TRPTrap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED, see Usage Fault Status Register.
[1]USERSETMPENDIf written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer.
[0]NONEBASETHRDENAWhen 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value.

System Handler Priority Registers

Use the three System Handler Priority Registers to prioritize the following system handlers:

  • memory manage

  • bus fault

  • usage fault

  • debug monitor

  • SVC

  • SysTick

  • PendSV.

System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault.

The register addresses, access types, and Reset states are:

Address

0xE000ED18, 0xE000ED1C , 0xE000ED20

Access

Read/write

Reset state

0x00000000

Figure 8.13 shows the fields of the System Handler Priority Registers.

Figure 8.13. System Handler Priority Registers bit assignments

Table 8.19 describes the fields of the System Handler Priority Registers.

Table 8.19. System Handler Priority Registers bit assignments

BitsFieldFunction
[31:24]PRI_N3Priority of system handler 7, 11, and 15. Reserved, SVCall, and SysTick.
[23:16]PRI_N2Priority of system handler 6, 10, and 14. Usage Fault, reserved, and PendSV.
[15:8]PRI_N1Priority of system handler 5, 9, and 13, Bus Fault, reserved, and reserved.
[7:0]PRI_NPriority of system handler 4, 8, and 12. Mem Manage, reserved, and Debug Monitor.

System Handler Control and State Register

Use the System Handler Control and State Register to:

  • enable or disable the system handlers

  • determine the pending status of bus fault, mem manage fault, and SVC

  • determine the active status of the system handlers.

If a fault condition occurs while its fault handler is disabled, the fault escalates to a Hard Fault.

The register address, access type, and Reset state are:

Address

0xE000ED24

Access

Read/write

Reset state

0x00000000

Figure 8.14 shows the fields of the System Handler and State Control Register.

Figure 8.14. System Handler Control and State Register bit assignments

Table 8.20 describes the fields of the System Handler Control Register.

Table 8.20. System Handler Control and State Register bit assignments

BitsFieldFunction
[31:19]-Reserved
[18]USGFAULTENASet to 0 to disable, else 1 for enabled.
[17]BUSFAULTENASet to 0 to disable, else 1 for enabled.
[16]MEMFAULTENASet to 0 to disable, else 1 for enabled.
[15]SVCALLPENDEDReads as 1 if SVCall is pended.
[14]BUSFAULTPENDED

Reads as 1 if BusFault is pended.

[13]MEMFAULTPENDEDReads as 1 if MemManage is pended.
[12]USGFAULTPENDEDRead as 1 if usage fault is pended
[11]SYSTICKACTReads as 1 if SysTick is active.
[10]PENDSVACTReads as 1 if PendSV is active.
[9]-Reserved
[8]MONITORACTReads as 1 if the Monitor is active.
[7]SVCALLACTReads as 1 if SVCall is active.
[6:4]-Reserved
[3]USGFAULTACTReads as 1 if UsageFault is active.
[2]-Reserved
[1]BUSFAULTACTReads as 1 if BusFault is active.
[0]MEMFAULTACTReads as 1 if MemManage is active.

The active bits indicate if any of the system handlers are active, running now, or stacked because of pre-emption. This information is used for debugging and is also used by the application handlers. The pend bits are only set when a fault that cannot be retried has been deferred because of late arrival of a higher priority interrupt.

Caution

You can write, clear, or set the active bits, but you must only do this with extreme caution. Clearing and setting these bits does not repair stack contents nor clean up other data structures. It is intended that context switchers use clearing and setting to save a thread’s context, even when in a fault handler. The most common case is to save the context of a thread that is in an SVCall handler or UsageFault handler, for undefined instruction and coprocessor emulation.

The model for doing this is to save the current state, switch out the stack containing the handler’s context, load the state of the new thread, switch in the new thread’s stacks, and then return to the thread. The active bit of the current handler must never be cleared, because the IPSR is not changed to reflect this. Only use it to change stacked active handlers.

As indicated, the SVCALLPENDED and BUSFAULTPENDED bits are set when the corresponding handler is held off by a late arriving interrupt. These bits are not cleared until the underlying handler is actually invoked. That is, if a stack error or vector read error occurs before the SVCall or BusFault handler is started, the bits are not cleared. This enables the push-error or vector-read-error handler to choose to clear them or retry.

Configurable Fault Status Registers

Use the three Configurable Fault Status Registers to obtain information about local faults. These registers include:

The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit.

The register addresses, access types, and Reset states are:

Address

0xE000ED28 Memory Manage Fault Status Register

0xE000ED29 Bus Fault Status Register

0xE000ED2A Usage Fault Status Register

Access

Read/write-one-to-clear

Reset state

0x00000000

Figure 8.15 shows the fields of the Configurable Fault Status Registers.

Figure 8.15. Configurable Fault Status Registers bit assignments

Memory Manage Fault Status Register

The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults.

The register address, access type, and Reset state are:

Address

0xE000ED28

Access

Read/write-one-to-clear

Reset state

0x00000000

Figure 8.16 shows the fields of the Memory Manage Fault Status Register.

Figure 8.16. Memory Manage Fault Register bit assignments

Table 8.21 describes the fields of the Memory Manage Fault Status Register.

Table 8.21. Memory Manage Fault Status Register bit assignments

BitsFieldFunction
[7]MMARVALID

Memory Manage Address Register (MMAR) address valid flag:

1 = valid fault address in MMAR. A later-arriving fault, such as a bus fault, can clear a memory manage fault.

0 = no valid fault address in MMAR.

If a MemManage fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems on return to a stacked active MemManage handler whose MMAR value has been overwritten.

[4]MSTKERRStacking from exception has caused one or more access violations. The SP is still adjusted and the values in the context area on the stack might be incorrect. The MMAR is not written.
[3]MUNSTKERRUnstack from exception return has caused one or more access violations. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The MMAR is not written.
[1]DACCVIOLData access violation flag. Attempting to load or store at a location that does not permit the operation sets the DACCVIOL flag. The return PC points to the faulting instruction. This error loads MMAR with the address of the attempted access.
[0]IACCVIOLInstruction access violation flag. Attempting to fetch an instruction from a location that does not permit execution sets the IACCVIOL flag. This occurs on any access to an XN region, even when the MPU is disabled or not present. The return PC points to the faulting instruction. The MMAR is not written.
Bus Fault Status Register

The flags in the Bus Fault Status Register indicate the cause of bus access faults.

The register address, access type, and Reset state are:

Address

0xE000ED29

Access

Read/write-one-to-clear

Reset state

0x00000000

Figure 8.17 shows the fields of the Bus Fault Status Register.

Figure 8.17. Bus Fault Status Register bit assignments

Table 8.22 describes the fields of the Bus Fault Status Register.

Table 8.22. Bus Fault Status Register bit assignments

BitsFieldFunction
[7]BFARVALID

This bit is set if the Bus Fault Address Register (BFAR) contains a valid address. This is true after a bus fault where the address is known. Other faults can clear this bit, such as a Mem Manage fault occurring later.

If a Bus fault occurs that is escalated to a Hard Fault because of priority, the Hard Fault handler must clear this bit. This prevents problems if returning to a stacked active Bus fault handler whose BFAR value has been overwritten.

[6:5]-Reserved.
[4]STKERRStacking from exception has caused one or more bus faults. The SP is still adjusted and the values in the context area on the stack might be incorrect. The BFAR is not written.
[3]UNSTKERRUnstack from exception return has caused one or more bus faults. This is chained to the handler, so that the original return stack is still present. SP is not adjusted from failing return and new save is not performed. The BFAR is not written.
[2]IMPRECISERRImprecise data bus error. It is a BusFault, but the Return PC is not related to the causing instruction. This is not a synchronous fault. So, if detected when the priority of the current activation is higher than the Bus Fault, it only pends. Bus fault activates when returning to a lower priority activation. If a precise fault occurs before returning to a lower priority exception, the handler detects both IMPRECISERR set and one of the precise fault status bits set at the same time. The BFAR is not written.
[1]PRECISERRPrecise data bus error return.
[0]IBUSERR

Instruction bus error flag:

1 = instruction bus error

0 = no instruction bus error.

The IBUSERR flag is set by a prefetch error. The fault stops on the instruction, so if the error occurs under a branch shadow, no fault occurs. The BFAR is not written.

Usage Fault Status Register

The flags in the Usage Fault Status Register indicate the following errors:

  • illegal combination of EPSR and instruction

  • illegal PC load

  • illegal processor state

  • instruction decode error

  • attempt to use a coprocessor instruction

  • illegal unaligned access.

The register address, access type, and Reset state are:

Address

0xE000ED2B

Access

Read/write clear

Reset state

0x00000000

Figure 8.18 shows the fields of the Usage Fault Status Register.

Figure 8.18. Usage Fault Status Register bit assignments

Table 8.23 describes the fields of the Usage Fault Status Register.

Table 8.23. Usage Fault Status Register bit assignments

BitsFieldFunction
[9]DIVBYZEROWhen DIV_0_TRP (see Configuration Control Register) is enabled and an SDIV or UDIV instruction is used with a divisor of 0, this fault occurs The instruction is executed and the return PC points to it. If DIV_0_TRP is not set, then the divide returns a quotient of 0.
[8]UNALIGNEDWhen UNALIGN_TRP is enabled (see Configuration Control Register), and there is an attempt to make an unaligned memory access, then this fault occurs.Unaligned LDM/STM/LDRD/STRD instructions always fault irrespective of the setting of UNALIGN_TRP.
[7:4]-Reserved.
[3]NOCPAttempt to use a coprocessor instruction. The processor does not support coprocessor instructions.
[2]INVPCAttempt to load EXC_RETURN into PC illegally. Invalid instruction, invalid context, invalid value. The return PC points to the instruction that tried to set the PC.
[1]INVSTATEInvalid combination of EPSR and instruction, for reasons other than UNDEFINED instruction. Return PC points to faulting instruction, with the invalid state.
[0]UNDEFINSTRThe UNDEFINSTR flag is set when the processor attempts to execute an undefined instruction. This is an instruction that the processor cannot decode. The return PC points to the undefined instruction.

Note

The fault bits are additive if more than one fault occurs before this register is cleared.

Hard Fault Status Register

Use the Hard Fault Status Register (HFSR) to obtain information about events that activate the Hard Fault handler.

The register address, access type, and Reset state are:

Address

0xE000ED2C

Access

Read/write-one-to-clear

Reset state

0x00000000

The HFSR is a write-clear register. This means that writing a 1 to a bit clears that bit. Figure 8.19 shows the fields of the Hard Fault Status Register.

Figure 8.19. Hard Fault Status Register bit assignments

Table 8.24 describes the fields of the Hard Fault Status Register.

Table 8.24. Hard Fault Status Register bit assignments

BitsFieldFunction
[31]DEBUGEVT

This bit is set if there is a fault related to debug.

This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated.

[30]FORCEDHard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled.The Hard Fault handler then has to read the other fault status registers to determine cause.
[29:2]-Reserved.
[1]VECTTBLThis bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction.
[0]-Reserved.

Debug Fault Status Register

Use the Debug Fault Status Register to monitor:

  • external debug requests

  • vector catches

  • data watchpoint match

  • BKPT instruction execution

  • halt requests.

Multiple flags in the Debug Fault Status Register can be set when multiple fault conditions occur. The register is read/write clear. This means that it can be read normally. Writing a 1 to a bit clears that bit.

Note

These bits are not set unless the event is caught. This means that it causes a stop of some sort. If halting debug is enabled, these events stop the processor into debug. If debug is disabled and the debug monitor is enabled, then this becomes a debug monitor handler call, if priority permits. If debug and the monitor are both disabled, some of these events are Hard Faults, and the DBGEVT bit is set in the Hard Fault status register, and some are ignored.

The register address, access type, and Reset state are:

Address

0xE000ED30

Access

Read/write-one-to-clear

Reset state

0x00000000

Figure 8.20 shows the fields of the Debug Fault Status Register.

Figure 8.20. Debug Fault Status Register bit assignments

Table 8.25 describes the fields of the Debug Fault Status Register.

Table 8.25. Debug Fault Status Register bit assignments

BitsFieldFunction
[31:5]-Reserved
[4]EXTERNAL

External debug request flag:

1 = EDBGRQ signal asserted

0 = EDBGRQ signal not asserted.

The processor stops on next instruction boundary.

[3]VCATCH

Vector catch flag:

1 = vector catch occurred

0 = no vector catch occurred.

When the VCATCH flag is set, a flag in one of the local fault status registers is also set to indicate the type of fault.

[2]DWTTRAP

Data Watchpoint and Trace (DWT) flag:

1 = DWT match

0 = no DWT match.

The processor stops at the current instruction or at the next instruction.

[1]BKPT

BKPT flag:

1 = BKPT instruction execution

0 = no BKPT instruction execution.

The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction.

[0]HALTED

Halt request flag:

1 = halt requested by NVIC, including step. The processor is halted on the next instruction.

0 = no halt request.

Memory Manage Fault Address Register

Use the Memory Manage Fault Address Register to read the address of the location that caused a Memory Manage Fault.

The register address, access type, and Reset state are:

Address

0xE000ED34

Access

Read/write

Reset state

Unpredictable

Table 8.26 describes the field of the Memory Manage Fault Address Register.

Table 8.26. Memory Manage Fault Address Register bit assignments

Bits FieldFunction
[31:0] ADDRESS Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault. See Memory Manage Fault Status Register.

Bus Fault Address Register

Use the Bus Fault Address Register to read the address of the location that generated a Bus Fault.

The register address, access type, and Reset state are:

Address

0xEEE0ED38

Access

Read/write

Reset state

Unpredictable

Table 8.27 describes the fields of the Bus Fault Address Register.

Table 8.27. Bus Fault Address Register bit assignments

BitsFieldFunction
[31:0]ADDRESSBus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault. See Bus Fault Status Register.

Auxiliary Fault Status Register

Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault information to software.

The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a single-cycle high level on an external pin causes the corresponding AFSR bit to become latched as one. The bit can only be cleared by writing a one to the corresponding AFSR bit.

When an AFSR bit is written or latched as one, an exception does not occur. If you require an exception, you must use an interrupt.

The register address, access type, and Reset state are:

Address

0xEEE0ED3C

Access

Read/write-clear

Reset state

0x00000000

describes the field of the AFSR.

Table 8.28. Auxiliary Fault Status Register bit assignments

BitsFieldFunction
[31:0]IMPDEFImplementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs. See Miscellaneous.

Software Trigger Interrupt Register

Use the Software Trigger Interrupt Register to pend an interrupt to trigger.

The register address, access type, and Reset state are:

Address

0xE000EF00

Access

Write-only

Reset state

0x00000000

Figure 8.21 shows the fields of the Software Trigger Interrupt Register.

Figure 8.21. Software Trigger Interrupt Register bit assignments

Table 8.29 describes the fields of the Software Trigger Interrupt Register.

Table 8.29. Software Trigger Interrupt Register bit assignments

BitsFieldFunction
[31:9]-Reserved.
[8:0]INTIDInterrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register.
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