5.7. Late-arriving

A late-arriving interrupt can pre-empt a previous interrupt if the first instruction of the previous ISR has not entered the Execute stage, and the late-arriving interrupt has a higher priority than the previous interrupt.

A late-arriving interrupt causes a new vector address fetch and ISR prefetch. State saving is not performed for the late-arriving interrupt because it has already been performed for the initial interrupt and so does not have to be repeated.

Figure 5.4 shows an example of late-arriving interrupts.

Figure 5.4. Late-arriving exception timing

In Figure 5.4, INTISR[8] pre-empts INTISR[2]. The state saving for INTISR[2] is already done and is not required to be repeated. Figure 5.4 shows the latest point at which INTISR[8] can pre-empt before the first instruction of the ISR for INTISR[2] enters Execute stage. A higher priority interrupt after that point is managed as a pre-emption.

Figure 5.4 shows the latest point at which INTISR[9] can pre-empt before the first instruction of the ISR for INTISR[8] enters Fetch stage. The ISR fetch for INTISR[8] is aborted when INTISR[9] is received, and the processor then initiates the vector fetch for INTISR[9]. A higher priority interrupt after that point is managed as pre-emption.

In the cycle that the ISR for INTISR[9] enters execute:

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