7.2. System power management

Writing to the System Control Register (see System Control Register ) controls the Cortex-M3 system power states. Table 7.1 shows the supported sleep modes.

Table 7.1.  Supported sleep modes

Sleep mechanism Description
Sleep-nowThe Wait For Interrupt (WFI) or the Wait For Event (WFE) instructions request the sleep-now model. These instructions cause the Nested Vectored Interrupt Controller (NVIC) to put the processor into the low-power state pending another exception.[1]
Sleep-on-exit

When the SLEEPONEXIT bit of the System Control Register is set, the processor enters the low-power state as soon as it exits the lowest priority ISR. The processor enters the low-power state without popping registers and a following exception is taken without having to push registers. The core stays in sleep state until another exception is pended. This is an automated WFI mode.

Note

Sleep-on-exit might return to base under various situations such as debug. Therefore, you must provide base code such as an idle loop or idle thread.

Deep-sleep

Deep-sleep is used in conjunction with Sleep-now and Sleep-on-exit. When the SLEEPDEEP bit of the System Control Register is set, the processor indicates to the system that deeper sleep is possible.

[1] The WFI instruction can complete even if no exception becomes active. Do not use it to detect the occurrence of an exception. WFI is normally used in an idle loop in the Thread mode. For more information on WFI, WFE, BASEPRI, and PRIMASK see the ARMv7-M Architecture Reference Manual.

The processor exports the following signals to indicate when the processor is sleeping:

SLEEPING

This signal is asserted when in Sleep-now or Sleep-on-exit modes, and indicates that the clock to the processor can be stopped. On receipt of a new interrupt, the NVIC de-asserts this signal, releasing the core from sleep. SLEEPING shows an example of SLEEPING usage.

SLEEPDEEP

This signal is asserted when in Sleep-now or Sleep-on-exit modes when the SLEEPDEEP bit of the System Control Register is set. This signal is routed to the clock manager and can gate the processor and system components including the Phase Locked Loop (PLL) to achieve greater power savings. On receipt of a new interrupt, the Nested Vectored Interrupt Controller (NVIC) deasserts this signal, and release core sleep when the clock manager indicates that the clock is stable. SLEEPDEEP shows an example of SLEEPDEEP usage.

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