Figure 7.2 shows an example of how to reduce power consumption by stopping the clock controller with SLEEPDEEP in the low-power state. When exiting low-power state, the LOCK signal indicates that the PLL is stable, and it is safe to enable the Cortex-M3 clock, ensuring that the processor is not re-started until the clocks are stable.

Figure 7.2. SLEEPDEEP power control example

To detect interrupts, the processor must receive the free-running FCLK in the low-power state. FCLK frequency can be reduced during SLEEPDEEP assertion.

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