Figure 7.1 shows an example of how to reduce power consumption by gating the HCLK clock to the processor with SLEEPING in the low-power state. If necessary, you can also use SLEEPING to gate other system components.

Figure 7.1. SLEEPING power control example

To detect interrupts, the processor must receive the free-running FCLK at all times. FCLK clocks:

FCLK frequency can be reduced during SLEEPING assertion.


Suppressing HCLK using the clock-gating scheme in Figure 7.1 prevents debug accesses. The CoreSight Debug Ports (DPs) provide a power up signal that enables the system to bypass the clock-gating logic in Figure 7.1.

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