17.2. CPU AHB trace macrocell interface port descriptions

Table 17.1 list the AHB interface ports.

Table 17.1. AHB interface ports

Port nameDirectionDescription
HTMDHADDR[31:0]Output32-bit address.
HTMDHTRANS[1:0]OutputOutput indicates the type of the current data transfer. Can be IDLE, NONSEQUENTIAL, OR SEQUENTIAL.
HTMDHSIZE[1:0] OutputIndicates the size of the access. Can be 8, 16, or 32 bits.
HTMDHBURST[2:0]OutputOutput indicates if the transfer is part of a burst.
HTMDHPROT[3:0]OutputProvides information on the access.
HTMDHWDATA[31:0] Output32-bit write data bus.
HTMDHWRITEOutputWrite not read.
HTMDHRDATA[31:0]OutputRead data bus.
HTMDHREADYOutputWhen HIGH indicates that a transfer has completed on the bus. The signal is driven LOW to extend a transfer.
HTMDHRESP[1:0]OutputThe transfer response status. OKAY or ERROR.
HTMDHADDR[31:0]Output32-bit address.
HTMDHTRANS[1:0]OutputOutput indicates the type of the current data transfer. Can be IDLE, NONSEQUENTIAL, OR SEQUENTIAL.
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