1.8. Instruction set summary

This section provides:

Table 1.1 lists the 16-bit Cortex-M3 instructions.

Table 1.1. 16-bit Cortex-M3 instruction summary

Operation Assembler

Add register value and C flag to register value

ADC <Rd>, <Rm>

Add immediate 3-bit value to register

ADD <Rd>, <Rn>, #<immed_3>

Add immediate 8-bit value to register

ADD <Rd>, #<immed_8>

Add low register value to low register value

ADD <Rd>, <Rn>, <Rm>

Add high register value to low or high register value

ADD <Rd>, <Rm>

Add 4* (immediate 8-bit value) with PC to register

ADD <Rd>, PC, #<immed_8> * 4

Add 4* (immediate 8-bit value) with SP to register

ADD <Rd>, SP, #<immed_8> * 4

Add 4* (immediate 7-bit value) to SPADD SP, #<immed_7> * 4

Bitwise AND register values

AND <Rd>, <Rm>

Arithmetic shift right by immediate number

ASR <Rd>, <Rm>, #<immed_5>

Arithmetic shift right by number in registerASR <Rd>, <Rs>

Branch conditional

B<cond> <target address>

Branch unconditionalB <target_address>

Bit clear

BIC <Rd>, <Rm>

Software breakpointBKPT <immed_8>

Branch with link

BL <Rm>

Branch with link and exchangeBLX <Rm>
Compare not zero and branchCBNZ <Rn>,<label>
Compare zero and branchCBZ <Rn>,<label>

Compare negation of register value with another register value

CMN <Rn>, <Rm>

Compare immediate 8-bit value

CMP <Rn>, #<immed_8>

Compare registers

CMP <Rn>, <Rm>

Compare high register to low or high register

CMP <Rn>, <Rm>

Change processor stateCPS <effect>, <iflags>
Copy high or low register value to another high or low registerCPY <Rd> <Rm>

Bitwise exclusive OR register values

EOR <Rd>, <Rm>

Condition the following instruction, Condition the following two instructions, Condition the following three instructions, Condition the following four instructions

IT <cond>

IT<x> <cond>

IT<x><y> <cond>

IT<x><y><z> <cond>

Multiple sequential memory word loads

LDMIA <Rn>!, <registers>

Load memory word from base register address + 5-bit immediate offset

LDR <Rd>, [<Rn>, #<immed_5> * 4]

Load memory word from base register address + register offsetLDR <Rd>, [<Rn>, <Rm>]
Load memory word from PC address + 8-bit immediate offsetLDR <Rd>, [PC, #<immed_8> * 4]
Load memory word from SP address + 8-bit immediate offsetLDR, <Rd>, [SP, #<immed_8> * 4]

Load memory byte [7:0] from register address + 5-bit immediate offset

LDRB <Rd>, [<Rn>, #<immed_5>]

Load memory byte [7:0] from register address + register offsetLDRB <Rd>, [<Rn>, <Rm>]

Load memory halfword [15:0] from register address + 5-bit immediate offset

LDRH <Rd>, [<Rn>, #<immed_5> * 2]

Load halfword [15:0] from register address + register offset

LDRH <Rd>, [<Rn>, <Rm>]

Load signed byte [7:0] from register address + register offset

LDRSB <Rd>, [<Rn>, <Rm>]

Load signed halfword [15:0] from register address + register offset

LDRSH <Rd>, [<Rn>, <Rm>]

Logical shift left by immediate number

LSL <Rd>, <Rm>, #<immed_5>

Logical shift left by number in registerLSL <Rd>, <Rs>

Logical shift right by immediate number

LSR <Rd>, <Rm>, #<immed_5>

Logical shift right by number in registerLSR <Rd>, <Rs>

Move immediate 8-bit value to register

MOV <Rd>, #<immed_8>

Move low register value to low register

MOV <Rd>, <Rn>

Move high or low register value to high or low register

MOV <Rd>, <Rm>

Multiply register values

MUL <Rd>, <Rm>

Move complement of register value to register

MVN <Rd>, <Rm>

Negate register value and store in register

NEG <Rd>, <Rm>

No operationNOP <c>

Bitwise logical OR register values

ORR <Rd>, <Rm>

Pop registers from stack

POP <registers>

Pop registers and PC from stack

POP <registers, PC>

Push registers onto stack

PUSH <registers>

Push LR and registers onto stack

PUSH <registers, LR>

Reverse bytes in word and copy to registerREV <Rd>, <Rn>
Reverse bytes in two halfwords and copy to registerREV16 <Rd>, <Rn>
Reverse bytes in low halfword [15:0], sign-extend, and copy to registerREVSH <Rd>, <Rn>

Rotate right by amount in register

ROR <Rd>, <Rs>

Subtract register value and C flag from register valueSBC <Rd>, <Rm>
Send eventSEV <c>

Store multiple register words to sequential memory locations

STMIA <Rn>!, <registers>

Store register word to register address + 5-bit immediate offset

STR <Rd>, [<Rn>, #<immed_5> * 4]

Store register word to register address

STR <Rd>, [<Rn>, <Rm>]

Store register word to SP address + 8-bit immediate offset

STR <Rd>, [SP, #<immed_8> * 4]

Store register byte [7:0] to register address + 5-bit immediate offset

STRB <Rd>, [<Rn>, #<immed_5>]

Store register byte [7:0] to register address

STRB <Rd>, [<Rn>, <Rm>]

Store register halfword [15:0] to register address + 5-bit immediate offset

STRH <Rd>, [<Rn>, #<immed_5> * 2]

Store register halfword [15:0] to register address + register offset

STRH <Rd>, [<Rn>, <Rm>]

Subtract immediate 3-bit value from register

SUB <Rd>, <Rn>, #<immed_3>

Subtract immediate 8-bit value from register value

SUB <Rd>, #<immed_8>

Subtract register values

SUB <Rd>, <Rn>, <Rm>

Subtract 4 (immediate 7-bit value) from SPSUB SP, #<immed_7> * 4
Operating system service call with 8-bit immediate call code

SVC <immed_8>

Extract byte [7:0] from register, move to register, and sign-extend to 32 bitsSXTB <Rd>, <Rm>
Extract halfword [15:0] from register, move to register, and sign-extend to 32 bitsSXTH <Rd>, <Rm>

Test register value for set bits by ANDing it with another register value

TST <Rn>, <Rm>

Extract byte [7:0] from register, move to register, and zero-extend to 32 bitsUXTB <Rd>, <Rm>
Extract halfword [15:0] from register, move to register, and zero-extend to 32 bitsUXTH <Rd>, <Rm>
Wait for eventWFE <c>
Wait for interruptWFI <c>

Table 1.2 lists the 32-bit Cortex-M3 instructions.

Table 1.2. 32-bit Cortex-M3 instruction summary

OperationAssembler
Add register value, immediate 12-bit value, and C bitADC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>
Add register value, shifted register value, and C bitADC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Add register value and immediate 12-bit valueADD{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Add register value and shifted register valueADD{S}.W <Rd>, <Rm>{, <shift>}
Add register value and immediate 12-bit valueADDW.W <Rd>, <Rn>, #<immed_12>
Bitwise AND register value with immediate 12-bit valueAND{S}.W <Rd>, <Rn>, #<modify_constant(immed_12>
Bitwise AND register value with shifted register valueAND{S}.W <Rd>, <Rn>, Rm>{, <shift>}
Arithmetic shift right by number in registerASR{S}.W <Rd>, <Rn>, <Rm>
Conditional branchB{cond}.W <label>
Clear bit fieldBFC.W <Rd>, #<lsb>, #<width>
Insert bit field from one register value into anotherBFI.W <Rd>, <Rn>, #<lsb>, #<width>
Bitwise AND register value with complement of immediate 12-bit valueBIC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Bitwise AND register value with complement of shifted register valueBIC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Branch with linkBL <label>
Branch with link (immediate)BL<c> <label>
Unconditional branchB.W <label>
Clear exclusive clears the local record of the executing processor that an address has had a request for an exclusive access.CLREX <c>
Return number of leading zeros in register valueCLZ.W <Rd>, <Rn>
Compare register value with two’s complement of immediate 12-bit valueCMN.W <Rn>, #<modify_constant(immed_12)>
Compare register value with two’s complement of shifted register valueCMN.W <Rn>, <Rm>{, <shift>}
Compare register value with immediate 12-bit valueCMP.W <Rn>, #<modify_constant(immed_12)>
Compare register value with shifted register valueCMP.W <Rn>, <Rm>{, <shift>}
Data memory barrierDMB <c>
Data synchronization barrierDSB <c>
Exclusive OR register value with immediate 12-bit valueEOR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register valueEOR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Instruction synchronization barrierISB <c>
Load multiple memory registers, increment after or decrement beforeLDM{IA|DB}.W <Rn>{!}, <registers>
Memory word from base register address + immediate 12-bit offsetLDR.W <Rxf>, [<Rn>, #<offset_12>]
Memory word to PC from register address + immediate 12-bit offset LDR.W PC, [<Rn>, #<offset_12>]
Memory word to PC from base register address immediate 8-bit offset, postindexedLDR.W PC, [Rn], #<+/-<offset_8>
Memory word from base register address immediate 8-bit offset, postindexedLDR.W <Rxf>, [<Rn>], #+/–<offset_8>
Memory word from base register address immediate 8-bit offset, preindexed

LDR.W <Rxf>, [<Rn>, #<+/–<offset_8>]!

LDRT.W <Rxf>, [<Rn>, #<offset_8>]

Memory word to PC from base register address immediate 8-bit offset, preindexedLDR.W PC, [<Rn>, #+/–<offset_8>]!
Memory word from register address shifted left by 0, 1, 2, or 3 placesLDR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word to PC from register address shifted left by 0, 1, 2, or 3 placesLDR.W PC, [<Rn>, <Rm>{, LSL #<shift>}]
Memory word from PC address immediate 12-bit offsetLDR.W <Rxf>, [PC, #+/–<offset_12>]
Memory word to PC from PC address immediate 12-bit offsetLDR.W PC, [PC, #+/–<offset_12>]
Memory byte [7:0] from base register address + immediate 12-bit offsetLDRB.W <Rxf>, [<Rn>, #<offset_12>]
Memory byte [7:0] from base register address immediate 8-bit offset, postindexedLDRB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory byte [7:0] from register address shifted left by 0, 1, 2, or 3 placesLDRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory byte [7:0] from base register address immediate 8-bit offset, preindexedLDRB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory byte from PC address immediate 12-bit offsetLDRB.W <Rxf>, [PC, #+/–<offset_12>]
Memory doubleword from register address 8-bit offset 4, preindexedLDRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Memory doubleword from register address 8-bit offset 4, postindexedLDRD.W <Rxf>, <Rxf2>, [<Rn>], #+/–<offset_8> * 4
Load register exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a registerLDREX<c> <Rt>,[<Rn>{,#<imm>}]
Load register exclusive halfword calculates an address from a base register value and an immediate offset, loads a halfword from memory, writes it to a registerLDREXH<c> <Rt>,[<Rn>{,#<imm>}]
Load register exclusive byte calculates an address from a base register value and an immediate offset, loads a byte from memory, writes it to a registerLDREXB<c> <Rt>,[<Rn>{,#<imm>}]
Memory halfword [15:0] from base register address + immediate 12-bit offsetLDRH.W <Rxf>, [<Rn>, #<offset_12>]
Memory halfword [15:0] from base register address immediate 8-bit offset, preindexedLDRH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory halfword [15:0] from base register address immediate 8-bit offset, postindexedLDRH.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory halfword [15:0] from register address shifted left by 0, 1, 2, or 3 placesLDRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory halfword from PC address immediate 12-bit offsetLDRH.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed byte [7:0] from base register address + immediate 12-bit offsetLDRSB.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed byte [7:0] from base register address immediate 8-bit offset, postindexedLDRSB.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory signed byte [7:0] from base register address immediate 8-bit offset, preindexedLDRSB.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory signed byte [7:0] from register address shifted left by 0, 1, 2, or 3 placesLDRSB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed byte from PC address immediate 12-bit offsetLDRSB.W <Rxf>, [PC, #+/–<offset_12>]
Memory signed halfword [15:0] from base register address + immediate 12-bit offsetLDRSH.W <Rxf>, [<Rn>, #<offset_12>]
Memory signed halfword [15:0] from base register address immediate 8-bit offset, postindexedLDRSH.W <Rxf>. [<Rn>], #+/-<offset_8>
Memory signed halfword [15:0] from base register address immediate 8-bit offset, preindexedLDRSH.W <Rxf>, [<Rn>, #<+/–<offset_8>]!
Memory signed halfword [15:0] from register address shifted left by 0, 1, 2, or 3 placesLDRSH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Memory signed halfword from PC address immediate 12-bit offsetLDRSH.W <Rxf>, [PC, #+/–<offset_12>]
Logical shift left register value by number in registerLSL{S}.W <Rd>, <Rn>, <Rm>
Logical shift right register value by number in registerLSR{S}.W <Rd>, <Rn>, <Rm>
Multiply two signed or unsigned register values and add the low 32 bits to a register valueMLA.W <Rd>, <Rn>, <Rm>, <Racc>
Multiply two signed or unsigned register values and subtract the low 32 bits from a register valueMLS.W <Rd>, <Rn>, <Rm>, <Racc>
Move immediate 12-bit value to registerMOV{S}.W <Rd>, #<modify_constant(immed_12)>
Move shifted register value to registerMOV{S}.W <Rd>, <Rm>{, <shift>}
Move immediate 16-bit value to top halfword [31:16] of registerMOVT.W <Rd>, #<immed_16>
Move immediate 16-bit value to bottom halfword [15:0] of register and clear top halfword [31:16]MOVW.W <Rd>, #<immed_16>
Move to register from statusMRS<c> <Rd>, <psr>
Move to status registerMSR<c> <psr>_<fields>,<Rn>
Multiply two signed or unsigned register valuesMUL.W <Rd>, <Rn>, <Rm>
No operationNOP.W
Logical OR NOT register value with immediate 12-bit valueORN{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR NOT register value with shifted register valueORN[S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Logical OR register value with immediate 12-bit valueORR{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Logical OR register value with shifted register valueORR{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Reverse bit orderRBIT.W <Rd>, <Rm>
Reverse bytes in wordREV.W <Rd>, <Rm>
Reverse bytes in each halfwordREV16.W <Rd>, <Rn>
Reverse bytes in bottom halfword and sign-extendREVSH.W <Rd>, <Rn>
Rotate right by number in registerROR{S}.W <Rd>, <Rn>, <Rm>
Rotate right with extendRRX{S}.W <Rd>, <Rm>
Subtract a register value from an immediate 12-bit valueRSB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract a register value from a shifted register valueRSB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value and C bit from register valueSBC{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value and C bit from register valueSBC{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Copy selected bits to register and sign-extendSBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Signed divideSDIV<c> <Rd>,<Rn>,<Rm>
Send eventSEV<c>
Multiply signed words and add signed-extended value to 2-register valueSMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two signed register valuesSMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Signed saturateSSAT.W <c> <Rd>, #<imm>, <Rn>{, <shift>}
Multiple register words to consecutive memory locationsSTM{IA|DB}.W <Rn>{!}, <registers>
Register word to register address + immediate 12-bit offsetSTR.W <Rxf>, [<Rn>, #<offset_12>]
Register word to register address immediate 8-bit offset, postindexedSTR.W <Rxf>, [<Rn>], #+/–<offset_8>
Register word to register address shifted by 0, 1, 2, or 3 placesSTR.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register word to register address immediate 8-bit offset, preindexed Store, preindexed

STR.W <Rxf>, [<Rn>, #+/-<offset_8>]{!}

STRT.W <Rxf>, [<Rn>, #<offset_8>]

Register byte [7:0] to register address immediate 8-bit offset, preindexedSTRB{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register byte [7:0] to register address + immediate 12-bit offsetSTRB.W <Rxf>, [<Rn>, #<offset_12>]
Register byte [7:0] to register address immediate 8-bit offset, postindexedSTRB.W <Rxf>, [<Rn>], #+/–<offset_8>
Register byte [7:0] to register address shifted by 0, 1, 2, or 3 placesSTRB.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Store doubleword, preindexedSTRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]{!}
Store doubleword, postindexedSTRD.W <Rxf>, <Rxf2>, [<Rn>, #+/–<offset_8> * 4]
Store register exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed.STREX <c> <Rd>,<Rt>,[<Rn>{,#<imm>}]
Store register exclusive byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressedSTREXB <c> <Rd>,<Rt>,[<Rn>]
Store register exclusive halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed.STREXH <c> <Rd>,<Rt>,[<Rn>]
Register halfword [15:0] to register address + immediate 12-bit offsetSTRH.W <Rxf>, [<Rn>, #<offset_12>]
Register halfword [15:0] to register address shifted by 0, 1, 2, or 3 placesSTRH.W <Rxf>, [<Rn>, <Rm>{, LSL #<shift>}]
Register halfword [15:0] to register address immediate 8-bit offset, preindexedSTRH{T}.W <Rxf>, [<Rn>, #+/–<offset_8>]{!}
Register halfword [15:0] to register address immediate 8-bit offset, postindexedSTRH.W <Rxf>, [<Rn>], #+/–<offset_8>
Subtract immediate 12-bit value from register valueSUB{S}.W <Rd>, <Rn>, #<modify_constant(immed_12)>
Subtract shifted register value from register valueSUB{S}.W <Rd>, <Rn>, <Rm>{, <shift>}
Subtract immediate 12-bit value from register valueSUBW.W <Rd>, <Rn>, #<immed_12>
Sign extend byte to 32 bitsSXTB.W <Rd>, <Rm>{, <rotation>}
Sign extend halfword to 32 bitsSXTH.W <Rd>, <Rm>{, <rotation>}
Table branch byteTBB [<Rn>, <Rm>]
Table branch halfwordTBH [<Rn>, <Rm>, LSL #1]
Exclusive OR register value with immediate 12-bit valueTEQ.W <Rn>, #<modify_constant(immed_12)>
Exclusive OR register value with shifted register valueTEQ.W <Rn>, <Rm>{, <shift}
Logical AND register value with 12-bit immediate valueTST.W <Rn>, #<modify_constant(immed_12)>
Logical AND register value with shifted register valueTST.W <Rn>, <Rm>{, <shift>}
Copy bit field from register value to register and zero-extend to 32 bitsUBFX.W <Rd>, <Rn>, #<lsb>, #<width>
Unsigned divideUDIV<c> <Rd>,<Rn>,<Rm>
Multiply two unsigned register values and add to a 2-register valueUMLAL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Multiply two unsigned register valuesUMULL.W <RdLo>, <RdHi>, <Rn>, <Rm>
Unsigned saturateUSAT <c> <Rd>, #<imm>, <Rn>{, <shift>}
Copy unsigned byte to register and zero-extend to 32 bitsUXTB.W <Rd>, <Rm>{, <rotation>}
Copy unsigned halfword to register and zero-extend to 32 bitsUXTH.W <Rd>, <Rm>{, <rotation>}
Wait for eventWFE.W
Wait for interruptWFI.W
Copyright © 2005, 2006 ARM Limited. All rights reserved.ARM DDI 0337E
Non-Confidential