1.2.1. Cortex-M3 hierarchy and implementation options

Figure 1.1 shows that the processor components exist in two levels of hierarchy. This represents the RTL hierarchy of the design. Four components, ETM, TPIU, SW/SWJ-DP, and ROM table, exist outside the Cortex-M3 level because these components are either optional, or there is flexibility in their implementation and use. Your implementation might differ from that shown in Figure 1.1. The possible implementation options are shown in:


The implementation options for the TPIU are:

  • If the ETM is present in your system, both of the input ports to the TPIU are present. Otherwise, only one port is used, saving the gate cost of one input FIFO.

  • Single or multiple TPIUs can trace a multi-core implementation.

  • You can replace the ARM TPIU block with a partner-specific CoreSight™ compliant TPIU.

  • In a production device, the TPIU might have been removed.


    There is no Cortex-M3 trace capability if the TPIU is removed.


The implementation options for the SW/SWJ-DP are:

  • Your implementation might contain either SW-DP or SWJ-DP.

  • You can replace the ARM SW-DP with a partner-specific CoreSight compliant SW-DP.

  • You can replace the ARM SWJ-DP with a partner-specific CoreSight compliant SWJ-DP.

  • You can include a partner-specific test interface in parallel with SW-DP or SWJ-DP.

ROM table

The ROM table is modified from that described in ROM memory table if:

  • Additional debug components have been added into the system.

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