2.3.2. Special-purpose Program Status Registers (xPSR)

Processor status at the system level breaks down into three categories:

They can be accessed as individual registers, a combination of any two from three, or a combination of all three using the Move to Register from Status (MRS) and MSR instructions.

Application PSR

The Application PSR (APSR) contains the condition code flags. Before entering an exception, the processor saves the condition code flags on the stack. You can access the APSR with the MSR(2) and MRS(2) instructions.

Figure 2.2 shows the fields of the APSR.

Figure 2.2. Application Program Status Register bit assignments

Table 2.1 describes the fields of the APSR.

Table 2.1. Application Program Status Register bit assignments

FieldNameDefinition
[31] N

Negative or less than flag:

1 = result negative or less than

0 = result positive or greater than.

[30] Z

Zero flag:

1 = result of 0

0 = nonzero result.

[29] C

Carry/borrow flag:

1 = carry or borrow

0 = no carry or borrow.

[28] V

Overflow flag:

1 = overflow

0 = no overflow.

[27]QSticky saturation flag.
[26:0]-Reserved.

Interrupt PSR

The Interrupt PSR (IPSR) contains the Interrupt Service Routine (ISR) number of the current exception activation.

Figure 2.2 shows the fields of the IPSR.

Figure 2.3. Interrupt Program Status Register bit assignments

Table 2.2 describes the fields of the IPSR.

Table 2.2. Interrupt Program Status Register bit assignments

FieldNameDefinition
[31:9] - Reserved.
[8:0] ISR NUMBER

Number of pre-empted exception.

Base level = 0

NMI = 2

SVCall = 11

INTISR[0] = 16

INTISR[1] = 17

.

.

.

INTISR[15] = 31

.

.

.

INTISR[239] = 255

Execution PSR

The Execution PSR (EPSR) contains two overlapping fields:

  • the Interruptible-Continuable Instruction (ICI) field for interrupted load multiple and store multiple instructions

  • the execution state field for the If-Then (IT) instruction, and the Thumb state bit (T-bit).

Interruptible-continuable instruction field

Load Multiple (LDM) operations and Store Multiple (STM) operations are interruptible. The ICI field of the EPSR holds the information required to continue the load or store multiple from the point that the interrupt occurred.

If-then state field

The IT field of the EPSR contain the execution state bits for the If-Then instruction.

Note

Because the ICI field and the IT field overlap, load or store multiples within an If-Then block cannot be interrupt-continued.

Figure 2.4 shows the fields of the EPSR.

Figure 2.4. Execution Program Status Register

The EPSR is not directly accessible. Two events can modify the EPSR:

  • an interrupt occurring during an LDM or STM instruction

  • execution of the If-Then instruction.

Table 2.3 describes the fields of the EPSR.

Table 2.3. Bit functions of the EPSR

Field Name Definition
[31:27]- Reserved.
[26:25], [15:10]ICI Interruptible-continuable instruction bits. When an interrupt occurs during an LDM or STM operation, the multiple operation stops temporarily. The EPSR uses bits [15:12] to store the number of the next register operand in the multiple operation. After servicing the interrupt, the processor returns to the register pointed to by [15:12] and resumes the multiple operation. If the ICI field points to a register that is not in the register list of the instruction, the processor continues with the next register in the list, if any.
[26:25], [15:10]IT If-Then bits. These are the execution state bits of the If-Then instruction. They contain the number of instructions in the if-then block and the conditions for their execution.
[24]T

The T-bit can be cleared using an interworking instruction where bit [0] of the written PC is 0. It can also be cleared by unstacking from an exception where the stacked T bit is 0.

Executing an instruction while the T bit is clear causes an INVSTATE exception.

[23:16]- Reserved.
[9:0]- Reserved.
Base register update in LDM and STM operations

There are cases when an LDM or STM updates the base register:

  • When the instruction specifies base register write-back, the base register changes to the updated address. An abort restores the original base value.

  • When the base register is in the register list of an LDM, and is not the last register in the list, the base register changes to the loaded value.

An LDM/STM is restarted rather than continued if:

  • the LDM/STM faults

  • the LDM/STM is inside an IT.

If an LDM has completed a base load, it is continued from before the base load.

Saved xPSR bits

On entering an exception, the processor saves the combined information from the three status registers on the stack.

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