5.12.2. Local faults and escalation

Local faults are categorized according to their cause. See Table 5.10. When enabled, local fault handlers process all normal faults. However, a local fault escalates to a Hard Fault when:

Table 5.10 lists the local faults.

Table 5.10. Faults

FaultBit nameHandlerNotesTrap enable bit
ResetReset causeResetAny form of reset.RESETVCATCH
Vector Read errorVECTTBLHardFaultBus error returned when reading the vector table entry.INTERR
uCode stack push errorSTKERRBusFault Failure when saving context using hardware - bus error returned.INTERR
uCode stack push errorMSTKERRMemManageFailure when saving context using hardware - MPU access violation.INTERR
uCode stack pop errorUNSTKERRBusFaultFailure when restoring context using hardware - bus error returned.INTERR
uCode stack pop errorMUNSKERRMemManageFailure when restoring context using hardware - MPU access violation.INTERR
Escalated to Hard FaultFORCEDHardFaultFault occurred and handler is equal or higher priority than current, including fault within fault when priority does not enable, or Configurable fault disabled. Includes SVC, BKPT and other kinds of faults.HARDERR
MPU mismatchDACCVIOLMemManageViolation or fault on MPU as a result of data access.MMERR
MPU mismatchIACCVIOL MemManageViolation or fault on MPU as a result of instruction address.MMERR
Pre-fetch errorIBUSERRBusFaultBus error returned because of instruction fetch. Faults only if makes it to execute. Branch shadow can fault and be ignored. BUSERR
Precise data bus errorPRECISERRBusFaultBus error returned because of data access, and was precise, points to instruction.BUSERR
Imprecise data bus errorIMPRECISERRBusFaultLate bus error because of data access. Exact instruction is no longer known. This is pended and not synchronous. It does not cause FORCED.BUSERR
No CoprocessorNOCPUsageFaultTruly does not exist, or not present bit.NOCPERR
Undefined InstructionUNDEFINSTRUsageFaultUnknown instruction.STATERR
Attempt to execute an instruction when in an invalid ISA state. For example, not ThumbINVSTATEUsageFaultAttempt to execute in an invalid EPSR state. For example, after a BX type instruction has changed state. This includes states after return from exception including inter-working states.STATERR
Return to PC=EXC_RETURN when not enabled or with invalid magic numberINVPCUsageFaultIllegal exit, caused either by an illegal EXC_RETURN value, an EXC_RETURN and stacked EPSR value mismatch, or an exit while the current EPSR is not contained in the list of currently active exceptions.STATERR
Illegal unaligned load or storeUNALIGNEDUsageFaultThis occurs when any load-store multiple instruction attempts to access a non-word aligned location. It can be enabled to occur for any load-store that is unaligned to its size using the UNALIGN_TRP bit.CHKERR
Divide By 0DIVBYZEROUsageFaultThis can be enabled to occur when SDIV or UDIV is executed with a divisor of 0, and the DIV_0_TRP bit is set.CHKERR
SVC-SVCallSystem request (Service Call).-

Table 5.11 shows debug faults.

Table 5.11. Debug faults

Fault Flag Notes

Trap enable bit

Internal halt requestHALTEDNVIC request from, for example, step, core halt-
BreakpointBKPTSW breakpoint from patched instruction or FPB-
WatchpointDWTTRAPWatchpoint match in DWT-
ExternalEXTERNALEDBGRQ line asserted-
Vector catchVCATCHVector catch triggered. Corresponding FSR contains the primary cause of the exception.VC_xxx bit(s) or RESETVCATCH set
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