6.3.1. Power-on reset

Figure 6.1 shows the reset signals for the macrocell.

Figure 6.1. Reset signals

You must apply power-on or cold reset to the processor when power is first applied to the system. In the case of power-on reset, the falling edge of the reset signal, PORESETn, does not have to be synchronous to HCLK. Because PORESETn is synchronized within the processor, you do not have to synchronize this signal. Figure 6.2 shows the application of power-on reset. Figure 6.3 shows the reset synchronizers within the processor.

Figure 6.2. Power-on reset

It is recommended that you assert the reset signals for at least three HCLK cycles to ensure correct reset behavior. Figure 6.3 shows the internal reset synchronization.


You must consider LOCKUP from the Cortex-M3 system for inclusion in any external watchdog circuitry when an external debugger is not attached.

Figure 6.3. Internal reset synchronization

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