6.3.2. System reset

A system or warm reset initializes the majority of the macrocell, excluding the NVIC debug logic, FPB, DWT, and ITM. System reset typically resets a system that has been operating for some time, for example, watchdog reset.

SYSRESETn must be synchronized external to the processor. Figure 6.3 shows the example reset synchronization provided in CortexM3Integration.

Cortex-M3 exports a signal, SYSRESETREQ, that is asserted when the SYSRESETREQ bit of the Application Interrupt and Reset Control Register is set. For example, you can use this as an input to a watchdog timer as shown in Figure 6.1.

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