11.4.1. FPB programmer’s model

Table 11.1 lists the flash patch registers.

Table 11.1. FPB register summary

NameTypeAddressDescription
FP_CTRLRead/write0xE0002000See Flash Patch Control Register
FP_REMAPRead/write0xE0002004See Flash Patch Remap Register
FP_COMP0Read/write0xE0002008See Flash Patch Comparator Registers
FP_COMP1Read/write0xE000200CSee Flash Patch Comparator Registers
FP_COMP2Read/write0xE0002010See Flash Patch Comparator Registers
FP_COMP3Read/write0xE0002014See Flash Patch Comparator Registers
FP_COMP4Read/write0xE0002018See Flash Patch Comparator Registers
FP_COMP5Read/write0xE000201CSee Flash Patch Comparator Registers
FP_COMP6Read/write0xE0002020See Flash Patch Comparator Registers
FP_COMP7Read/write0xE0002024See Flash Patch Comparator Registers
PID4Read-only0xE0002FD0Value 0x04
PID5Read-only0xE0002FD4Value 0x00
PID6Read-only0xE0002FD8Value 0x00
PID7Read-only0xE0002FDCValue 0x00
PID0Read-only0xE0002FE0Value 0x03
PID1Read-only0xE0002FE4Value 0xB0
PID2Read-only0xE0002FE8Value 0x0B
PID3Read-only0xE0002FECValue 0x00
CID0Read-only0xE0002FF0Value 0x0D
CID1Read-only0xE0002FF4Value 0xE0
CID2Read-only0xE0002FF8Value 0x05
CID3Read-only0xE0002FFCValue 0xB1

Flash Patch Control Register

Use the Flash Patch Control Register to enable the flash patch block.

The register address, access type, and Reset state are:

Address

0xE0002000

Access

Read/write

Reset state

Bit [0] (ENABLE) is reset to 1'b0.

Figure 11.2 shows the fields of the Flash Patch Control Register.

Figure 11.2. Flash Patch Control Register bit assignments

Table 11.2 describes the fields of the Flash Patch Control Register.

Table 11.2. Flash Patch Control Register bit assignments

BitsFieldFunction
[31:15]-Reserved. Read As Zero. Write Ignored.
[14:12]NUM_CODE2Number of full banks of code comparators, sixteen comparators per bank. Where less than sixteen code comparators are provided, the bank count is zero, and the number present indicated by NUM_CODE. This read only field contains 3'b000 to indicate 0 banks for Cortex-M3 processor.
[11:8]NUM_LITNumber of literal slots field. This read only field contains b0010 to indicate that there are two literal slots.
[7:4]NUM_CODE1Number of code slots field. This read only field contains b0110 to indicate that there are six code slots.
[3:2]-Reserved.
[1]KEYKey field. To write to the Flash Patch Control Register, you must write a 1 to this write-only bit.
[0]ENABLE

Flash patch unit enable bit:

1 = flash patch unit enabled

0 = flash patch unit disabled.

Reset clears the ENABLE bit.

Note

If the TIEOFF_FPBEN define is uncommented in CM3Defs.v during implementation, it is not possible to set ENABLE.

Flash Patch Remap Register

Use the Flash Patch Remap Register to provide the location in System space where a matched address is remapped. The REMAP address is 8-word aligned, with one word allocated to each of the eight FPB comparators.

A comparison match remaps to:

{3’b001, REMAP, COMP[2:0], HADDR[1:0]}

where:

  • 3’b001 hardwires the remapped access to system space

  • REMAP is the 24-bit, 8-word aligned remap address

  • COMP is the matching comparator. See Table 11.3.

Table 11.3. COMP mapping

COMP[2:0]ComparatorDescription
000FP_COMP0Instruction comparator
001FP_COMP1Instruction comparator
010FP_COMP2Instruction comparator
011FP_COMP3Instruction comparator
100FP_COMP4Instruction comparator
101FP_COMP5Instruction comparator
110FP_COMP6Literal comparator
111FP_COMP7Literal comparator
  • HADDR[1:0] is the two Least Significant Bits (LSBs) of the original address. HADDR[1:0] is always 2’b00 for instruction fetches.

The register address, access type, and Reset state are:

Address

0xE0002004

Access

Read/write

Reset state

This register is not reset

Figure 11.3 shows the fields of the Flash Patch Remap Register.

Figure 11.3. Flash Patch Remap Register bit assignments

Table 11.4 describes the fields of the Flash Patch Remap Register.

Table 11.4. Flash Patch Remap Register bit assignments

BitsFieldFunction
[31:29]-Reserved. Read as b001. Hardwires the remap to the system space.
[28:5]REMAPRemap base address field.
[4:0]-Reserved. Read As Zero. Write Ignored.

Flash Patch Comparator Registers

Use the Flash Patch Comparator Registers to store the values to compare with the PC address.

The register address, access type, and Reset state are:

Access

Read/write

Address

0xE0002008, 0xE000200C, 0xE0002010, 0xE0002014, 0xE0002018, 0xE000201C, 0xE0002020, 0xE0002024

Reset state

Bit [0] (ENABLE) is reset to 1'b0.

Figure 11.4 shows the fields of the Flash Patch Comparator Registers.

Figure 11.4. Flash Patch Comparator Registers bit assignments

Table 11.5 describes the fields of the Flash Patch Comparator Registers.

Table 11.5. Flash Patch Comparator Registers bit assignments

BitsFieldFunction
[31:30]REPLACE

This selects what happens when the COMP address is matched.It is interpreted as:b00 = remap to remap address. See FP_REMAPb01 = set BKPT on lower halfword, upper is unaffectedb10 = set BKPT on upper halfword, lower is unaffectedb11 = set BKPT on both lower and upper halfwords.Settings other than b00 are only valid for instruction comparators. Literal comparators ignore non-b00 settings.

Address remapping only takes place for the b00 setting.

[29]-Reserved
[28:2]COMPComparison address.
[1]- Reserved.
[0]ENABLE

Compare and remap enable for Flash Patch Comparator Register n:

1 = Flash Patch Comparator Register n compare and remap enabled

0 = Flash Patch Comparator Register n compare and remap disabled.

The ENABLE bit of FP_CTRL must also be set to enable comparisons.Reset clears the ENABLE bit.

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