11.5.1. Summary and description of the DWT registers

Table 11.6 lists the DWT registers.

Table 11.6. DWT register summary

NameTypeAddress

Reset value

Description
DWT_CTRLRead/write0xE00010000x00000000See DWT Control Register
DWT_CYCCNTRead/write0xE00010040x00000000See DWT Current PC Sampler Cycle Count Register
DWT_CPICNTRead/write0xE0001008-See DWT CPI Count Register
DWT_EXCCNTRead/write0xE000100C-See DWT Exception Overhead Count Register
DWT_SLEEPCNTRead/write0xE0001010-See DWT Sleep Count Register
DWT_LSUCNTRead/write0xE0001014-See DWT LSU Count Register
DWT_FOLDCNTRead/write0xE0001018-See DWT Fold Count Register
DWT_PCSRRead-only0xE000101C-See DWT Program Counter Sample Register
DWT_COMP0Read/write0xE0001020-See DWT Comparator Registers
DWT_MASK0Read/write0xE0001024-See DWT Mask Registers 0-3
DWT_FUNCTION0Read/write0xE00010280x00000000See DWT Function Registers 0-3
DWT_COMP1Read/write0xE0001030-See DWT Comparator Registers
DWT_MASK1Read/write0xE0001034-See DWT Mask Registers 0-3
DWT_FUNCTION1Read/write0xE00010380x00000000See DWT Function Registers 0-3
DWT_COMP2Read/write0xE0001040-See DWT Comparator Registers
DWT_MASK2Read/write0xE0001044-See DWT Mask Registers 0-3
DWT_FUNCTION2Read/write0xE00010480x00000000See DWT Function Registers 0-3
DWT_COMP3Read/write0xE0001050-See DWT Comparator Registers
DWT_MASK3Read/write0xE0001054 -See DWT Mask Registers 0-3
DWT_FUNCTION3Read/write0xE0001058 0x00000000See DWT Function Registers 0-3
PID4Read-only0xE0001FD00x04Value 0x04
PID5Read-only0xE0001FD40x00Value 0x00
PID6Read-only0xE0001FD80x00Value 0x00
PID7Read-only0xE0001FDC0x00Value 0x00
PID0Read-only0xE0001FE00x02Value 0x02
PID1Read-only0xE0001FE40xB0Value 0xB0
PID2Read-only0xE0001FE80x1BValue 0x1B
PID3Read-only0xE0001FEC0x00Value 0x00
CID0Read-only0xE0001FF00x0DValue 0x0D
CID1Read-only0xE0001FF40xE0Value 0xE0
CID2Read-only0xE0001FF80x05Value 0x05
CID3Read-only0xE0001FFC0xB1Value 0xB1

DWT Control Register

Use the DWT Control Register to enable the DWT unit.

The register address, access type, and Reset state are:

Address

0xE0001000

Access

Read/write

Reset state

0x40000000

Figure 11.5 shows the fields of the DWT Control Register.

Figure 11.5. DWT Control Register bit assignments

Table 11.7 describes the fields of the DWT Control Register.

Table 11.7. DWT Control Register bit assignments

BitsFieldFunction
[31:28]NUMCOMPNumber of comparators field. This read-only field contains b0100 to indicate four comparators.
[27:23]-Reserved.
[22]CYCEVTEN

Enables Cycle count event. Emits an event when the POSTCNT counter triggers it. See CYCTAP (bit [9]) and POSTPRESET, bits [4:1], for details.

1 = Cycle count events enabled

0 = Cycle count events disabled.This event is only emitted if PCSAMPLENA, bit [12], is disabled.

PCSAMPLENA overrides the setting of this bit.

Reset clears the CYCEVTENA bit.

[21]FOLDEVTENA

Enables Folded instruction count event. Emits an event when DWT_FOLDCNT overflows (every 256 cycles of folded instructions). A folded instruction is one that does not incur even one cycle to execute. For example, an IT instruction is folded away and so does not use up one cycle.

1 = Folded instruction count events enabled.

0 = Folded instruction count events disabled.

Reset clears the FOLDEVTENA bit.

[20]LSUEVTENA

Enables LSU count event. Emits an event when DWT_LSUCNT overflows (every 256 cycles of LSU operation). LSU counts include all LSU costs after the initial cycle for the instruction.

1 = LSU count events enabled.

0 = LSU count events disabled.

Reset clears the LSUEVTENA bit.

[19]SLEEPEVTENA

Enables Sleep count event. Emits an event when DWT_SLEEPCNT overflows (every 256 cycles that the processor is sleeping).

1 = Sleep count events enabled.

0 = Sleep count events disabled.

Reset clears the SLEEPEVTENA bit.

[18]EXCEVTENA

Enables Interrupt overhead event. Emits an event when DWT_EXCCNT overflows (every 256 cycles of interrupt overhead).

1 = Interrupt overhead event enabled.

0 = Interrupt overhead event disabled.

Reset clears the EXCEVTENA bit.

[17]CPIEVTENA

Enables CPI count event. Emits an event when DWT_CPICNT overflows (every 256 cycles of multi-cycle instructions).

1 = CPI counter events enabled.

0 = CPI counter events disabled.

Reset clears the CPIEVTENA bit.

[16]EXCTRCENA

Enables Interrupt event tracing:

1 = interrupt event trace enabled

0 = interrupt event trace disabled.

Reset clears the EXCEVTENA bit.

[15:13]-Reserved
[12]PCSAMPLEENA

Enables PC Sampling event. A PC sample event is emitted when the POSTCNT counter triggers it. See CYCTAP, bit [9], and POSTPRESET, bits [4:1], for details. Enabling this bit overrides CYCEVTENA (bit [20]).

1 = PC Sampling event enabled.

0 = PC Sampling event disabled.

Reset clears the PCSAMPLENA bit.

[11:10]SYNCTAP

Feeds a synchronization pulse to the ITM SYNCENA control. The value selected here picks the rate (approximately 1/second or less) by selecting a tap on the DWT_CYCCNT register. To use synchronization (heartbeat and hot-connect synchronization), CYCCNTENA must be set to 1, SYNCTAP must be set to one of its values, and SYNCENA must be set to 1.

0b00 = Disabled. No synch counting.0b01 = Tap at CYCCNT bit 24.0b10 = Tap at CYCCNT bit 26.0b11 = Tap at CYCCNT bit 28.

[9] CYCTAP

Selects a tap on the DWT_CYCCNT register. These are spaced at bits [6] and [10]:

CYCTAP = 0 selects bit [6] to tap

CYCTAP = 1 selects bit [10] to tap.

When the selected bit in the CYCCNT register changes from 0 to 1 or 1 to 0, it emits into the POSTCNT, bits [8:5], post-scalar counter. That counter then counts down. On a bit change when post-scalar is 0, it triggers an event for PC sampling or CYCEVTCNT.

[8:5]POSTCNT

Post-scalar counter for CYCTAP.

When the selected tapped bit changes from 0 to 1 or 1 to 0, the post scalar counter is down-counted when not 0.

If 0, it triggers an event for PCSAMPLENA or CYCEVTENA use. It also reloads with the value from POSTPRESET (bits [4:1]).

[4:1]POSTPRESET

Reload value for POSTCNT, bits [8:5], post-scalar counter.

If this value is 0, events are triggered on each tap change (a power of 2, such as 1<<6 or 1<<10).

If this field has a non-0 value, this forms a count-down value, to be reloaded into POSTCNT each time it reaches 0. For example, a value 1 in this register means an event is formed every other tap change.

[0]CYCCNTENAEnable the CYCCNT counter. If not enabled, the counter does not count and no event is generated for PS sampling or CYCCNTENA. In normal use, the debugger must initialize the CYCCNT counter to 0.

Note

The TRCENA bit of the Debug Exception and Monitor Control Register must be set before you can use the DWT. See Debug Exception and Monitor Control Register.

Note

The DWT is enabled independently from the ITM. If you enable the DWT to emit events, you must also enable the ITM.

DWT Current PC Sampler Cycle Count Register

Use the DWT Current PC Sampler Cycle Count Register to count the number of core cycles. This count can measure elapsed execution time.

The register address, access type, and Reset state are:

Address

0xE0001004

Access

Read-only

Reset state

0x00000000

Table 11.8 describes the fields of the DWT Current PC Sampler Cycle Count Register.

Table 11.8. DWT Current PC Sampler Cycle Count Register bit assignments

BitsFieldFunction
[31:0]CYCCNT

Current PC Sampler Cycle Counter count value. When enabled, this counter counts the number of core cycles, except when the core is halted.

CYCCNT is a free running counter, counting upwards. It wraps around to 0 on overflow.

The debugger must initialize this to 0 when first enabling.

This is a free-running counter. The counter has three functions:

  • When PCSAMPLENA is set, the PC is sampled and emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.

  • When CYCEVTENA is set (and PCSAMPLENA is clear), an event is emitted when the selected tapped bit changes value (0 to 1 or 1 to 0) and any post-scalar value counts to 0.

  • Applications and debuggers can use the counter to measure elapsed execution time. By subtracting a start and an end time, an application can measure time between in-core clocks (other than when Halted in debug). This is valid to 232 core clock cycles (for example, almost 86 seconds at 50MHz).

DWT CPI Count Register

Use the DWT CPI Count Register to count the total number of instruction cycles beyond the first cycle.

The register address, access type, and Reset state are:

Address

0xE0001008

Access

Read-write

Reset state

-

Figure 11.6 shows the fields of the DWT CPI Count Register.

Figure 11.6. DWT CPI Count Register bit assignments

Table 11.9 describes the fields of the DWT CPI Count Register.

Table 11.9. DWT CPI Count Register bit assignments

BitsFieldFunction
[31:8]- Reserved.
[7:0]CPICNT

Current CPI counter value. Increments on the additional cycles (the first cycle is not counted) required to execute all instructions except those recorded by DWT_LSUCNT. This counter also increments on all instruction fetch stalls.

If CPIEVTENA is set, an event is emitted when the counter overflows.

Clears to 0 on enabling.

DWT Exception Overhead Count Register

Use the DWT Exception Overhead Count Register to count the total cycles spent in interrupt processing.

The register address, access type, and Reset state are:

Address

0xE000100C

Access

Read-write

Reset state

-

Figure 11.7 shows the fields of the DTW Exception Overhead Count Register.

Figure 11.7. DWT Exception Overhead Count Register bit assignments

Table 11.10 describes the fields of the DWT Exception Overhead Count Register.

Table 11.10. DWT Exception Overhead Count Register bit assignments

BitsFieldFunction
[31:8]-Reserved.
[7:0]EXCCNT

Current interrupt overhead counter value. Counts the total cycles spent in interrupt processing (for example entry stacking, return unstacking, pre-emption). An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled.

Clears to 0 on enabling.

DWT Sleep Count Register

Use the DWT Sleep Count Register to count the total number of cycles during which the processor is sleeping.

The register address, access type, and Reset state are:

Address

0xE0001010

Access

Read-write

Reset state

-

Figure 11.8 shows the fields of the DTW Sleep Count Register.

Figure 11.8. DWT Sleep Count Register bit assignments

Table 11.11 describes the fields of the DWT Sleep Count Register.

Table 11.11. DWT Sleep Count Register bit assignments

BitsFieldFunction
[31:8]-Reserved.
[7:0]SLEEPCNTSleep counter. Counts the number of cycles during which the processor is sleeping. An event is emitted on counter overflow (every 256 cycles). This counter initializes to 0 when enabled.

Note

SLEEPCNT is clocked using FCLK. It is possible that the frequency of FCLK might be reduced while the processor is sleeping to minimize power consumption. This means that sleep duration must be calculated with the frequency of FCLK during sleep.

DWT LSU Count Register

Use the DWT LSU Count Register to count the total number of cycles during which the processor is processing an LSU operation beyond the first cycle.

The register address, access type, and Reset state are:

Address

0xE0001014

Access

Read/write

Reset state

-

Figure 11.9 describes the fields of the DWT LSU Count Register.

Figure 11.9. DWT LSU Count Register bit assignments

Table 11.12 describes the fields of the DWT LSU Count Register.

Table 11.12. DWT LSU Count Register bit assignments

BitsFieldFunction
[31:8]-Reserved.
[7:0]LSUCNT

LSU counter. This counts the total number of cycles that the processor is processing an LSU operation. The initial execution cost of the instruction is not counted.

For example, an LDR that takes two cycles to complete increments this counter one cycle. Equivalently, an LDR that stalls for two cycles (and so takes four cycles), increments this counter three times. An event is emitted on counter overflow (every 256 cycles).

Clears to 0 on enabling.

DWT Fold Count Register

Use the DWT Fold Count Register to count the total number of folded instructions. This counts 1 for each instruction that takes 0 cycles.

The register address, access type, and Reset state are:

Address

0xE0001018

Access

Read/write

Reset state

-

Figure 11.10 describes the fields of the DWT Fold Count Register.

Figure 11.10. DWT Fold Count Register bit assignments

Table 11.13 describes the fields of the DWT Fold Count Register.

Table 11.13. DWT Fold Count Register bit assignments

BitsFieldFunction
[31:8]-Reserved.
[7:0]FOLDCNTThis counts the total number folded instructions. This counter initializes to 0 when enabled.

DWT Program Counter Sample Register

Use the DWT Program Counter Sample Register (PCSR) to enable coarse-grained software profiling using a debug agent, without changing the currently executing code.

If the core is not in debug state, the value returned is the instruction address of a recently executed instruction.

If the core is in debug state, the value returned is 0xFFFFFFFF.

The register address, access type, and Reset state are:

Address

0xE000101C

Access

Read-only

Reset state

Unpredictable

Table 11.14 describes the field of the DWT PCSR.

Table 11.14. DWT Program Counter Sample Register bit assignments

BitsFieldFunction
[31:0]EIASAMPLEExecution instruction address sample, or 0xFFFFFFFF if the core is halted.

DWT Comparator Registers

Use the DWT Comparator Registers 0-3 to write the values that trigger watchpoint events.

The register address, access type, and Reset state are:

Address

0xE0001020, 0xE0001030, 0xE0001040, 0xE0001050

Access

Read/write

Reset state

-

Table 11.15 describes the field of DWT Comparator Registers 0-3.

Table 11.15. DWT Comparator Registers 0-3 bit assignments

FieldNameDefinition
[31:0]COMP

Data value to compare against PC and the data address as given by DWT_FUNCTIONx.

DWT_COMP0 can also compare against the value of the PC Sampler Counter (DWT_CYCCNT).

DWT_COMP1 can also compare against data values so that data matching can be performed (DATAVMATCH).

DWT Mask Registers 0-3

Use the DWT Mask Registers 0-3 to apply a mask to data addresses when matching against COMP.

The register address, access type, and Reset state are:

Address

0xE0001024, 0xE0001034, 0xE0001044, 0xE0001054

Access

Read/write

Reset state

-

Figure 11.11 shows the fields of DWT Mask Registers 0-3.

Figure 11.11. DWT Mask Registers 0-3 bit assignments

Table 11.16 describes the fields of DWT Mask Registers 0-3.

Table 11.16. DWT Mask Registers 0-3 bit assignments

BitsFieldFunction
[31:4]-Reserved.
[3:0]MASK

Mask on data address when matching against COMP. This is the size of the ignore mask.

So, ~0<<MASK forms the mask against the address to use. That is, DWT matching is performed as:(ADDR & (~0 << MASK)) == COMP

However, the actual comparison is slightly more complex to enable matching an address wherever it appears on a bus. So, if COMP is 3, this matches a word access of 0, because 3 would be within the word.

DWT Function Registers 0-3

Use the DWT Function Registers 0-3 to control the operation of the comparator. Each comparator can:

  • Match against either the PC or the data address. This is controlled by CYCMATCH. This function is only available for comparator 0 (DWT_COMP0).

  • Perform data value comparisons if associated address comparators have performed an address match. This function is only available for comparator 1 (DWT_COMP1).

  • Emit data or PC couples, trigger the ETM, or generate a watchpoint depending on the operation defined by FUNCTION.

The register address, access type, and Reset state are:

Address

0xE0001028, 0xE0001038, 0xE0001048, 0xE0001058

Access

Read/write

Address

0x00000000

Figure 11.12 shows the fields of DWT Function Registers 0-3.

Figure 11.12. DWT Function Registers 0-3 bit assignments

Table 11.17 describes the fields of DWT Function Registers 0-3.

Table 11.17. Bit functions of DWT Function Registers 0-3

BitsFieldFunction
[31:25]-Reserved.
[24]MATCHEDThis bit is set when the comparator matches, and indicates that the operation defined by FUNCTION has occurred since this bit was last read. This bit is cleared on read.
[23:20]-Reserved.
[19:16]DATAVADDR1Identity of a second linked address comparator for data value matching when DATAVMATCH == 1 and LNK1ENA == 1.
[15:12]DATAVADDR0Identity of a linked address comparator for data value matching when DATAVMATCH == 1.
[11:10]DATAVSIZE

Defines the size of the data in the COMP register that is to be matched:

00 = byte

01 = halfword

10 = word

11 = Unpredictable.

[9]LNK1ENA

Read-only:

0 = DATAVADDR1 not supported

1 = DATAVADDR1 supported (enabled).

[8]DATAVMATCH

This bit is only available in comparator 1. When DATAVMATCH is set, this comparator performs data value compares.

The comparators given by DATAVADDR0 and DATAVADDR1provide the address for the data comparison. If DATAVMATCH is set in DWT_FUNCTION1, the FUNCTION setting for the comparators given by DATAVADDR0 and DATAVADDR1 are overridden and those comparators only provide the address match for the data comparison.

[7]CYCMATCHOnly available in comparator 0. When set, this comparator compares against the clock cycle counter.
[6]-Reserved.
[5]EMITRANGE

Emit range field. Reserved to permit emitting offset when range match occurs. Reset clears the EMITRANGE bit. PC sampling is not supported when EMITRANGE is enabled.

EMITRANGE only applies for:

FUNCTION = b0001, b0010, and b0011.

[4]-Reserved.
[3:0]FUNCTIONSee Table 11.18 for FUNCTION settings.

Table 11.18 describes the function settings of the DWT Function Registers.

Table 11.18. Settings for DWT Function Registers

ValueFunction
b0000Disabled
b0001

EMITRANGE = 0, sample and emit PC through ITM

EMITRANGE = 1, emit address offset through ITM

b0010

EMITRANGE = 0, emit data through ITM on read and write.

EMITRANGE = 1, emit data and address offset through ITM on read or write.

b0011

EMITRANGE = 0, sample PC and data value through ITM on read or write.

EMITRANGE = 1, emit address offset and data value through ITM on read or write.

b0100Watchpoint on PC match.
b0101Watchpoint on read.
b0110Watchpoint on write.
b0111Watchpoint on read or write.
b1000ETM trigger on PC match
b1001ETM trigger on read
b1010ETM trigger on write
b1011ETM trigger on read or write
b1100Reserved
b1101Reserved
b1110Reserved
b1111Reserved

Note

  • If the ETM is not fitted, then ETM trigger is not possible.

  • Data value is only sampled for accesses that do not fault (MPU or bus fault). The PC is sampled irrespective of any faults. The PC is only sampled for the first address of a burst.

  • FUNCTION is overridden for comparators given by DATAVADDR0 and DATAVADDR1 in DWT_FUNCTION1if DATAVMATCH is also set in DWT_FUNCTION1. The comparators given by DATAVADDR0 and DATAVADDR1 can then only perform address comparator matches for comparator 1 data matches.

  • If the TIEOFF_DMATCH define is uncommented in CM3Defs.v during implementation it is not possible to set DATAVADDR0, DATAVADDR1, or DATAVMATCH in DWT_FUNCTION1. This means that the data matching functionality is not available in the implementation. Test the availability of data matching by writing and reading the DATAVMATCH bit in DWT_FUNCTION1. If it is not settable then data matching is unavailable.

  • PC match is not recommended for watchpoints because it stops after the instruction. It mainly guards and triggers the ETM.

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