11.6.1. Summary and description of the ITM registers

Note

TRCENA of the Debug Exception and Monitor Control Register must be enabled before you program or use the ITM, see Debug Exception and Monitor Control Register.

Table 11.19 lists the ITM registers.

Table 11.19. ITM register summary

NameTypeAddress

Reset value

Description
Stimulus Ports 0-31Read/write

0xE0000000-

0xE000007C

-See ITM Stimulus Ports 0-31
Trace EnableRead/write0xE0000E000x00000000See ITM Trace Enable Register
Trace PrivilegeRead/write0xE0000E400x00000000See ITM Trace Privilege Register
Trace Control RegisterRead/write0xE0000E800x00000000See ITM Trace Control Register
Integration WriteWrite-only0xE0000EF80x00000000See ITM Integration Write Register
Integration ReadRead-only0xE0000EFC0x00000000See ITM Integration Read Register
Integration Mode ControlRead/write 0xE0000F000x00000000See ITM Integration Mode Control Register
Lock Access RegisterWrite-only 0xE0000FB0 0x00000000See ITM Lock Access Register
Lock Status RegisterRead-only0xE0000FB4 0x00000003See ITM Lock Status Register
PID4Read-only0xE0000FD00x00000004Value 0x04
PID5Read-only0xE0000FD40x00000000Value 0x00
PID6Read-only0xE0000FD80x00000000Value 0x00
PID7Read-only0xE0000FDC0x00000000Value 0x00
PID0Read-only0xE0000FE00x00000001Value 0x01
PID1Read-only0xE0000FE40x000000B0Value 0xB0
PID2Read-only0xE0000FE80x0000001BValue 0x1B
PID3Read-only0xE0000FEC0x00000000Value 0x00
CID0Read-only0xE0000FF00x0000000DValue 0x0D
CID1Read-only0xE0000FF40x000000E0Value 0xE0
CID2Read-only0xE0000FF80x00000005Value 0x05
CID3Read-only0xE0000FFC0x000000B1Value 0xB1

Note

ITM registers are fully accessible in privileged mode. In user mode, all registers can be read, but only the Stimulus Registers and Trace Enable Registers can be written, and only when the corresponding Trace Privilege Register bit is set. Invalid user mode writes to the ITM registers are discarded.

ITM Stimulus Ports 0-31

Each of the 32 stimulus ports has its own address. A write to one of these locations causes data to be written into the FIFO if the corresponding bit in the Trace Enable Register is set. Reading from any of the stimulus ports returns the FIFO status in bit [0]:

  • 0 = full

  • 1 = not full.

The polled FIFO interface does not provide an atomic read-modify-write, so you must use the Cortex-M3 exclusive monitor if a polled printf is used concurrently with ITM usage by interrupts or other threads. The following polled code guarantees stimulus is not lost by polled access to the ITM:

; r0 = Value to write to port
; r1 and r2 = Temporary scratch registers
	MOV r1, #0xE0000000	      ; r1 = Stimulus port base
Retry   LDREX r2, [r1, #Port*4]			  ; Load FIFO full status
	CMP r2, #0			; Compare with full
	ITT NE			; If (not full)
	STREXNE r2, [r1, #Port*4]		; Try sending value to port
	CMPNE r2, #1		        ; and check for failure
	BEQ Retry		        ; If full or failed then retry

ITM Trace Enable Register

Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port.

The register address, access type, and Reset state are:

Access

Read/write

Address

0xE0000E00

Reset

0x00000000

Table 11.20 describes the field of the ITM Trace Enable Register.

Table 11.20. ITM Trace Enable Register bit assignments

BitsFieldFunction
[31:0]STIMENABit mask to enable tracing on ITM stimulus ports. One bit per stimulus port.

Note

Privileged writes are accepted to this register if ITMENA is set. User writes are accepted to this register if ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.

ITM Trace Privilege Register

Use the ITM Trace Privilege Register to enable an operating system to control which stimulus ports are accessible by user code.

Note

You can only write to this register in privileged mode.

The register address, access type, and Reset state are:

Access

Read/write

Address

0xE0000E40

Reset

0x00000000

Figure 11.13 shows the ITM Trace Privilege Register bit assignments.

Figure 11.13. ITM Trace Privilege Register bit assignments

Table 11.21 describes the fields of the ITM Trace Privilege Register.

Table 11.21.  ITM Trace Privilege Register bit assignments

BitsFieldFunction
[31:4]-Reserved.
[3:0]PRIVMASK

Bit mask to enable tracing on ITM stimulus ports:

bit [0] = stimulus ports [7:0]

bit [1] = stimulus ports [15:8]

bit [2] = stimulus ports [23:16]

bit [3] = stimulus ports [31:24].

ITM Trace Control Register

Use this register to configure and control ITM transfers.

Note

You can only write to this register in privilege mode.

The register address, access type, and Reset state are:

Access

Read/write

Address

0xE0000E80

Reset

0x00000000

Figure 11.14 shows the ITM Control Register bit assignments.

Figure 11.14. ITM Trace Control Register bit assignments

Table 11.22 describes the fields of the ITM Control Register.

Table 11.22. ITM Trace Control Register bit assignments

BitsFieldFunction
[31:24]-0b00000000.
[23]BUSYSet when ITM events present and being drained
[22:16]ATBIDATB ID for CoreSight system.
[15:10]-0b000000.
[9:8]TSPrescale

Timestamp prescaler:

0b00 = no prescaling

0b01 = divide by 4

0b10 = divide by 16

0b11 = divide by 64.

[7:5]-Reserved.
[4]SWOENAEnable SWV behavior – count on TPIUEMIT and TPIUBAUD.
[3]DWTENAEnables the DWT stimulus.
[2]SYNCENAEnables sync packets for TPIU.
[1]TSENA

Enables differential timestamps. Differential timestamps are emitted when a packet is written to the FIFO with a non-zero timestamp counter, and when the timestamp counter overflows.

Timestamps are emitted during idle times after a fixed number of cycles. This provides a time reference for packets and inter-packet gaps.

[0]ITMENAEnable ITM. This is the master enable, and must be set before ITM Stimulus and Trace Enable registers can be written.

Note

DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSSEN bit must be set.

ITM Integration Write Register

Use this register to determine the behavior of the ATVALIDM bit.

Figure 11.15 shows the ITM Integration Write Register bit assignments.

Figure 11.15. ITM Integration Write Register bit assignments

Table 11.23 describes the fields of the ITM Integration Write Register.

Table 11.23. ITM Integration Write Register bit assignments

BitsFieldFunction
[31:1]-Reserved
[0]ATVALIDM

When the integration mode is set:

0 = ATVALIDM clear

1 = ATVALIDM set.

Note

Bit [0] drives ATVALIDM when mode is set.

ITM Integration Read Register

Use this register to read the value on ATREADYM

Figure 11.16 shows the ITM Integration Read Register bit assignments.

Figure 11.16. ITM Integration Read Register bit assignments

Table 11.24 describes the fields of the ITM Integration Read Register.

Table 11.24.  ITM Integration Read Register bit assignments

BitsFieldFunction
[31:1]-Reserved
[0]ATREADYMValue on ATREADYM

ITM Integration Mode Control Register

Use this register to enable write accesses to the Control Register.

Figure 11.17 shows the ITM Integration Mode Control Register bit assignments.

Figure 11.17. ITM Integration Mode Control bit assignments

Table 11.25 describes the fields of the ITM Integration Mode Control Register

Table 11.25. ITM Integration Mode Control Register bit assignments

BitsFieldFunction
[31:1]-Reserved
[0]INTEGRATION

0 = ATVALIDM normal

1 = ATVALIDM driven from Integration Write Register

ITM Lock Access Register

Use this register to prevent write accesses to the Control Register.

Table 11.26 describes the fields of the ITM Lock Access Register

Table 11.26. ITM Lock Access Register bit assignments

BitsFieldFunction
[31:0]Lock AccessA privileged write of 0xC5ACCE55 enables more write access to Control Register 0xE00::0xFFC. An invalid write removes write access.

ITM Lock Status Register

Use this register to enable write accesses to the Control Register.

Figure 11.18 shows the ITM Lock Status Register bit assignments.

Figure 11.18. ITM Lock Status Register bit assignments

Table 11.27 describes the fields of the ITM Lock Status Register

Table 11.27. ITM Lock Status Register bit assignments

BitsFieldFunction
[31:3]-Reserved.
[2]ByteAccYou cannot implement 8-bit lock accesses.
[1]AccessWrite access to component is blocked. All writes are ignored, reads are permitted.
[0]PresentIndicates that a lock mechanism exists for this component.
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