15.1.2. ETM inputs and outputs

This section describes the ETM inputs and outputs:

Table 15.1. ETM core interface inputs and outputs

NameDescriptionQualified byDirection
ETMIA[31:1]Core instruction address bus.ETMIVALIDInput
ETMIVALIDCurrent instruction data represents an instruction.-Input
ETMDVALIDCurrent instruction data represents an instruction.-Input
ETMICCFAILInstruction failed its condition code.ETMIVALIDInput
ETMIBRANCHInstruction is a branch target.ETMIVALIDInput
ETMIINDBRInstruction is an indirect branch target.ETMIBRANCHInput
ETMFLUSHPC modified before next instruction.-Input
ETMISTALLIndicates that the last instruction signalled by the core has not yet entered execute.-Input
ETMFINDBRPC modified by an indirect operation.ETMFLUSHInput
ETMINTSTAT[2:0]Exception entry and exit.-Input
ETMINTNUM[8:0]Exception type.ETMINTSTATInput
ETMCANCELException is a canceling exception.ETMINTSTATInput
COREHALTCore is halted.-Input
DWTMATCH [3:0]Indicates that the Data Watchpoint and Trace (DWT) trigger units have matched the conditions currently present on the address, data and control buses.-Input
DWTINOTD[3:0]Indicates that the DWT trigger units are performing comparisons on PC value (set) or data address (clear).-Input

Table 15.2. Miscellaneous configuration inputs

NameDescriptionDirectionClock domain
NIDENNon invasive debug enableInputHCLK
EXTIN[1:0]External input resourceInputHCLK
MAXEXTIN[1:0]Maximum supported external inputsInputHCLK
CGBYPASSBypass architectural clock gating cellInputCLK


One of the EXTIN inputs to the ETM could be driven from the LOCKUP output from the core to enable trace capture to stop, or trigger if a lockup condition occurs. The EXTIN inputs are not synchronized in the ETM. If they are not driven from the ETM clock, then you must synchronize them outside the ETM.

Table 15.3. Trace port signals

NameDescriptionDirectionClock domain
ATDATAM[7:0]Eight-bit trace dataOutputHCLK
ATIDM[6:0]Trace Source IDOutputHCLK
ATREADYMIndicates that the Trace Port is able to accept the Data on ATDATAInputHCLK
AFREADYMIndicates that the ETM FIFO is emptyOutputHCLK

Table 15.4. Other signals

NameDescriptionDirectionClock domain
FIFOPEEK[9:0]For validation purposes onlyOutputHCLK
ETMPWRUPIndicates that the ETM is powered upOutputHCLK
ETMTRIGOUTTrigger occurred status signalOutputHCLK
ETMDBGRQDebug request to coreOutputHCLK
ETMENETM traceport enabledOutputHCLK

Table 15.5. Clocks and resets

HCLKClock for ETM logic which should be connected to the same FCLK as Cortex-M3.Input
HRESETnPower on reset for the HCLK domain. Must not be the same as core HCLK reset (SYSRESETn).Input

Table 15.6. APB interface signals

NameDescriptionDirectionClock domain
PSELAPB device selectInputCLK
PENABLEAPB control signalInputCLK
PADDR[11:2]APB Address BusInputCLK
PWRITEAPB Transfer direction (!Read/Write)InputCLK
PWDATA[31:0]APB Write Data BusInputCLK
PRDATA[31:0]APB Read Data BusOutputCLK
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