15.6.3. Description of ETM registers

An additional description of some of the ETM registers is given in the following sections. See the ARM Embedded Trace Macrocell Architecture Specification for more information.

ETM Control Register

The ETM Control Register controls general operation of the ETM, such as whether tracing is enabled.

Reset value: 0x00002411

Implemented bits: [21], [17:16], [13], [11:4], [0]

All other bits RAZ, ignore writes.

Configuration Code Register

The ETM Configuration Code Register enables the debugger to read the implementation-specific configuration of the ETM.

Reset value: 0x8C800000

Bits [22:20] are fixed at 0 and not supplied by the ASIC. Bits [18:17] are supplied by the MAXEXTIN[1:0] input bus, and read the lower value of MAXEXTIN and the number 2 (the number of EXTINs). This indicates:

  • software accesses supported

  • trace start/stop block present

  • no CID comparators

  • FIFOFULL logic is present

  • no external outputs

  • 0-2 external inputs (controlled by MAXEXTIN)

  • no sequencer

  • no counters

  • no MMDs

  • no data comparators

  • no address comparator pairs.

System Configuration Register

The System Configuration Register shows the ETM features supported by the ASIC.

Reset value: 0x00020D09

Bits [11:10] are implemented as normal. Bits [9], [2:0] are fixed as 4’b0001.

TraceEnable Control 1 Register

The TraceEnable Control 1 Register is one of the registers that configures TraceEnable.

Only bit [25] is implemented. It controls the start/stop resource controls tracing.

ETM ID Register

The ETM ID Register holds the ETM architecture variant, and precisely defines the programmer’s model for the ETM.

Reset value: 0x4114F241

This indicates:

  • ARM implementor

  • special branch encoding, affects bits [7:6] of each byte

  • Thumb-2 supported

  • core family is found elsewhere

  • ETMv3.4

  • implementation revision 1.

Configuration Code Extension Register

The Configuration Code Extension Register holds additional bits for ETM configuration code. It describes the extended external inputs.

Reset value: 0x00018800

This register indicates:

  • start/stop block uses embedded In Circuit Emulator (ICE) inputs

  • four embedded ICE inputs

  • no data comparisons supported

  • all registers are readable

  • no extended external input supported.

Power Down Status Register

The Power Down Status Register (PDSR) indicates whether the ETM is powered up or not.

Reset value: 0x00000001

Only bit [0] is implemented. It indicates whether the ETM debug power domain is powered up or not:

  • 0 = ETM debug power domain not powered up

  • 1 = ETM debug power domain powered up.

Note

If the ETM is not powered up, the ETM registers are not accessible.

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