19.2.1. Input port timing parameters

Table 19.1 shows the timing parameters for the miscellaneous input ports.

Table 19.1. Miscellaneous input ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty10%PORESETn
Clock uncertainty10%SYSRESETn
Clock uncertainty50%BIGEND
Clock uncertainty50%EDBGRQ
Clock uncertainty50%STCLK
Clock uncertainty50%STCALIB[25:0]
Clock uncertainty50%RXEV
Clock uncertainty50%AUXFAULT[31:0]
Clock uncertainty50%IFLUSH
Clock uncertainty50%PPBLOCK[5:0]

Table 19.2 shows the timing parameters for the interrupt input ports.

Table 19.2. Interrupt input ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%INTISR[239:0]
Clock uncertainty50%INTNMI
Clock uncertainty20%VECTADDR[9:0]
Clock uncertainty20%VECTADDREN

Table 19.3 shows the timing parameters for the Advanced High-performance Bus (AHB) ports.

Table 19.3. AHB input ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty10%DNOTITRANS
Clock uncertainty50%HRDATAI[31:0]
Clock uncertainty50%HREADYI
Clock uncertainty50%HRESPI[1:0]
Clock uncertainty50%HRDATAD[31:0]
Clock uncertainty50%HREADYD
Clock uncertainty50%HRESPD[1:0]
Clock uncertainty50%EXRESPD
Clock uncertainty50%HRDATAS[31:0]
Clock uncertainty50%HREADYS
Clock uncertainty50%HRESPS[1:0]
Clock uncertainty50%EXRESPS

Table 19.4 shows the timing parameter for the Private Peripheral Bus (PPB) port.

Table 19.4. PPB input port timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%PRDATA[31:0]

Table 19.5 shows the timing parameters for the debug input ports.

Table 19.5. Debug input ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty10%nTRST
Clock uncertainty50%SWDITMS
Clock uncertainty50%TDI
Clock uncertainty50%DAPRESETn
Clock uncertainty50%DAPSEL
Clock uncertainty50%DAPEN
Clock uncertainty50%DAPENABLE
Clock uncertainty50%DAPCLKEN
Clock uncertainty50%DAPWRITE
Clock uncertainty50%DAPABORT
Clock uncertainty50%DAPADDR[31:0]
Clock uncertainty50%DAPWDATA[31:0]
Clock uncertainty50%ATREADY

Table 19.6 shows the timing parameters for the test input ports.

Table 19.6. Test input ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty10%SE
Clock uncertainty10%SI
Clock uncertainty10%RSTBYPASS
Clock uncertainty10%CGBYPASS
Clock uncertainty10%WSII
Clock uncertainty10%WSOI

Table 19.7 shows the timing parameters for the Embedded Trace Macrocell (ETM).

Table 19.7. ETM input port timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty30%ETMPWRUP

Table 19.8 shows the timing parameters for the miscellaneous output ports.

Table 19.8. Miscellaneous output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%LOCKUP
Clock uncertainty50%SLEEPING
Clock uncertainty50%SLEEPDEEP
Clock uncertainty50%SYSRESETREQ
Clock uncertainty50%BRCHSTAT[3:0]
Clock uncertainty50%HALTED
Clock uncertainty50%TXEV
Clock uncertainty50%ATIDITM[6:0]
Clock uncertainty50%CURRPRI[7:0]
Clock uncertainty70%TRCENA

Table 19.9 shows the timing parameters for the AHB output ports.

Table 19.9. AHB output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%HTRANSI[1:0]
Clock uncertainty50%HSIZEI[2:0]
Clock uncertainty50%HPROTI[3:0]
Clock uncertainty50%MEMATTRI[1:0]
Clock uncertainty50%HBURSTI[2:0]
Clock uncertainty50%HADDRI[31:0]
Clock uncertainty50%HMASTERD[1:0]
Clock uncertainty50%HTRANSD[1:0]
Clock uncertainty50%HSIZED[2:0]
Clock uncertainty50%HPROTD[3:0]
Clock uncertainty50%MEMATTRD[1:0]
Clock uncertainty50%EXREQD
Clock uncertainty50%HBURSTD[2:0]
Clock uncertainty50%HADDRD[31:0]
Clock uncertainty50%HWDATAD[31:0]
Clock uncertainty50%HWRITED
Clock uncertainty50%HMASTERS[1:0]
Clock uncertainty50%HTRANSS[1:0]
Clock uncertainty50%HSIZES[2:0]
Clock uncertainty50%HPROTS[3:0]
Clock uncertainty50%MEMATTRS[1:0]
Clock uncertainty50%EXREQS
Clock uncertainty50%HBURSTS[2:0]
Clock uncertainty50%HMASTLOCKS
Clock uncertainty50%HADDRS[31:0]
Clock uncertainty50%HWDATAS[31:0]
Clock uncertainty50%HWRITES

Table 19.10 shows the timing parameters for the PPB output ports.

Table 19.10. PPB output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%PADDR31
Clock uncertainty50%PADDR[19:2]
Clock uncertainty50%PSEL
Clock uncertainty50%PENABLE
Clock uncertainty50%PWRITE
Clock uncertainty50%PWDATA[31:0]

Table 19.11 shows the timing parameters for the debug interface output ports.

Table 19.11. Debug interface output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%SWV
Clock uncertainty50%TRACECLK
Clock uncertainty50%TRACEDATA[3:0]
Clock uncertainty50%TDO
Clock uncertainty50%SWDO
Clock uncertainty50%nTDOEN
Clock uncertainty50%SWDOEN
Clock uncertainty50%DAPREADY
Clock uncertainty50%DAPSLVERR
Clock uncertainty50%DAPRDATA[31:0]
Clock uncertainty50%ATVALID
Clock uncertainty50%AFREADY
Clock uncertainty50%ATDATA[7:0]

Table 19.12 shows the timing parameters for the ETM interface output ports.

Table 19.12. ETM interface output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty30%ETMTRIGGER[3:0]
Clock uncertainty30%ETMTRIGINOTD[3:0]
Clock uncertainty30%ETMIVALID
Clock uncertainty30%ETMDVALID
Clock uncertainty30%ETMFOLD
Clock uncertainty30%ETMCANCEL
Clock uncertainty30%ETMIA[31:1]
Clock uncertainty30%ETMICCFAIL
Clock uncertainty30%ETMIBRANCH
Clock uncertainty30%ETMIINDBR
Clock uncertainty30%ETMFLUSH
Clock uncertainty30%ETMFINDBR
Clock uncertainty30%ETMINTSTAT[2:0]
Clock uncertainty30%ETMINTNUM[8:0]
Clock uncertainty30%ETMISTALL
Clock uncertainty30%DSYNC

Table 19.13 shows the timing parameters for the AHB Trace Macrocell (HTM) interface output ports.

Table 19.13. HTM interface output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty50%HTMDHADDR[31:0]
Clock uncertainty50%HTMDHTRANS[1:0]
Clock uncertainty50%HTMDHSIZE[2:0]
Clock uncertainty50%HTMDHBURST[2:0]
Clock uncertainty50%HTMDHPROT[3:0]
Clock uncertainty50%HTMDHWDATA[31:0]
Clock uncertainty50%HTMDHWRITE
Clock uncertainty50%HTMDHRDATA[31:0]
Clock uncertainty50%HTMDHREADY
Clock uncertainty50%HTMDHRESP[1:0]

Table 19.14 shows the timing parameters for the test output ports.

Table 19.14. Test output ports timing parameters

Input delay Min.Input delay Max.Signal name
Clock uncertainty10%SO
Clock uncertainty10%WSOO
Clock uncertainty10%WSIO
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