Cortex ™-M3 TechnicalReference Manual

Revision: r1p1


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the Cortex-M3 processor
Feedback on this manual
1. Introduction
1.1. About the processor
1.2. Components, hierarchy, and implementation
1.2.1. Cortex-M3 hierarchy and implementation options
1.2.2. Processor core
1.2.3. NVIC
1.2.4. Bus Matrix
1.2.5. FPB
1.2.6. DWT
1.2.7. ITM
1.2.8. MPU
1.2.9. ETM
1.2.10. TPIU
1.2.11. SW/SWJ-DP
1.3. Configurable options
1.3.1. Interrupts
1.3.2. MPU
1.3.3. DWT
1.3.4. ETM
1.3.5. AHB Trace Macrocell interface
1.4. Execution pipeline stages
1.5. Prefetch Unit
1.6. Branch target forwarding
1.6.1. Zero waitstate
1.6.2. Zero waitstate, registered fetch interface(ICODE)
1.6.3. One wait state flash
1.6.4. One wait state flash, registered fetchinterface (ICODE)
1.6.5. Two wait states flash
1.7. Store buffers
1.8. Instruction set summary
1.9. Product revisions
1.9.1. Differences in functionality betweenr0p0 and r1p0
1.9.2. Differences in functionality betweenr1p0 and r1p1
2. Programmer’s Model
2.1. About the programmer’s model
2.1.1. Operating modes
2.1.2. Operating states
2.2. Privileged access and user access
2.2.1. Main stack and process stack
2.3. Registers
2.3.1. General-purpose registers
2.3.2. Special-purpose Program Status Registers (xPSR)
2.4. Data types
2.5. Memory formats
2.6. Instruction set
3. System Control
3.1. Summary of processor registers
3.1.1. Nested Vectored Interrupt Controllerregisters
3.1.2. Core debug registers
3.1.3. System debug registers
3.1.4. Debug interface port registers
3.1.5. Memory Protection Unit registers
3.1.6. Trace Port Interface Unit registers
3.1.7. Embedded Trace Macrocell registers
4. Memory Map
4.1. About the memory map
4.2. Bit-banding
4.2.1. Directly accessing an alias region
4.2.2. Directly accessing a bit-band region
4.3. ROM memory table
5. Exceptions
5.1. About the exception model
5.2. Exception types
5.3. Exception priority
5.3.1. Priority levels
5.3.2. Priority grouping
5.4. Privilege and stacks
5.4.1. Stacks
5.4.2. Privilege
5.5. Pre-emption
5.5.1. Stacking
5.6. Tail-chaining
5.7. Late-arriving
5.8. Exit
5.8.1. Exception exit
5.8.2. Returning the processor from an ISR
5.9. Resets
5.9.1. Vector Table and Reset
5.9.2. Intended boot-up sequence
5.10. Exception control transfer
5.11. Setting up multiple stacks
5.12. Abort model
5.12.1. Hard Fault
5.12.2. Local faults and escalation
5.12.3. Fault status registers and fault address registers
5.13. Activation levels
5.14. Flowcharts
5.14.1. Interrupt handling
5.14.2. Pre-emption
5.14.3. Return
6. Clocking and Resets
6.1. Clocking
6.2. Resets
6.3. Cortex-M3 reset modes
6.3.1. Power-on reset
6.3.2. System reset
6.3.3. SWJ-DP reset
6.3.4. SW-DP reset
6.3.5. Normal operation
7. Power Management
7.1. About power management
7.2. System power management
7.2.1. SLEEPING
7.2.2. SLEEPDEEP
8. Nested Vectored Interrupt Controller
8.1. About the NVIC
8.2. NVIC programmer’s model
8.2.1. NVIC register map
8.2.2. NVIC register descriptions
8.3. Level versus pulse interrupts
9. Memory Protection Unit
9.1. About the MPU
9.2. MPU programmer’s model
9.2.1. Summary of the MPU registers
9.2.2. Description of the MPU registers
9.2.3. Accessing the MPU using the aliasregisters
9.2.4. Sub-Regions
9.3. MPU access permissions
9.4. MPU aborts
9.5. Updating an MPU region
9.5.1. Updating an MPU region using CP15 equivalent code
9.5.2. Updating an MPU region using two or three words
9.6. Interrupts and updating the MPU
10. Core Debug
10.1. About core debug
10.1.1. Halt mode debugging
10.1.2. Exiting core debug
10.2. Core debug registers
10.2.1. Debug Halting Control and Status Register
10.2.2. Debug Core Register Selector Register
10.2.3. Debug Core Register Data Register
10.2.4. Debug Exception and Monitor ControlRegister
10.3. Core debug access example
10.4. Using application registers in coredebug
11. System Debug
11.1. About system debug
11.2. System debug access
11.3. System debug programmer’s model
11.4. FPB
11.4.1. FPB programmer’s model
11.5. DWT
11.5.1. Summary and description of the DWT registers
11.6. ITM
11.6.1. Summary and description of the ITM registers
11.7. AHB-AP
11.7.1. AHB-AP transaction types
11.7.2. Summary and description of the AHB-APregisters
12. Debug Port
12.1. About the DP
13. Trace Port Interface Unit
13.1. About the TPIU
13.1.1. TPIU block diagrams
13.1.2. TPIU components
13.1.3. TPIU inputs and outputs
13.2. TPIU registers
13.2.1. Summary of the TPIU registers
13.2.2. Description of the TPIU registers
13.3. Serial wire output connection
13.3.1. A dedicated pin can be used for TRACESWO
13.3.2. SWO shared with TRACEPORT
13.3.3. SWO Shared with JTAG-TDO
14. Bus Interface
14.1. About bus interfaces
14.2. AMBA 3 compliance
14.3. ICode bus interface
14.3.1. Branch status signal
14.4. DCode bus interface
14.4.1. Exclusives
14.4.2. Memory attributes
14.5. System interface
14.5.1. Unaligned accesses
14.5.2. Bit-band accesses
14.5.3. Flash Patch remapping
14.5.4. Exclusives
14.5.5. Memory attributes
14.5.6. Pipelined instruction fetches
14.6. Unifying the code buses
14.7. External private peripheral interface
14.8. Access alignment
14.9. Unaligned accesses that cross regions
14.10. Bit-band accesses
14.11. Write buffer
14.12. Memory attributes
14.13. AHB timing characteristics
15. Embedded Trace Macrocell
15.1. About the ETM
15.1.1. ETM block diagram
15.1.2. ETM inputs and outputs
15.2. Data tracing
15.3. ETM resources
15.3.1. Periodic synchronization
15.3.2. Data and instruction address compare resources
15.3.3. FIFO functionality
15.4. Trace output
15.5. ETM architecture
15.5.1. Restartable instructions
15.5.2. Exception return
15.5.3. Exception tracing
15.6. ETM programmer’s model
15.6.1. Advanced Peripheral Bus interface
15.6.2. List of ETM registers
15.6.3. Description of ETM registers
16. Embedded Trace Macrocell Interface
16.1. About the ETM interface
16.2. CPU ETM interface port descriptions
16.3. Branch status interface
17. AHB Trace Macrocell Interface
17.1. About the AHB trace macrocell interface
17.2. CPU AHB trace macrocell interfaceport descriptions
18. Instruction Timing
18.1. About instruction timing
18.2. Processor instruction timings
18.3. Load-store timings
19. AC Characteristics
19.1. Processor timing parameters
19.2. Processor timing parameters
19.2.1. Input port timing parameters
A. Signal Descriptions
A.1. Clocks
A.2. Resets
A.3. Miscellaneous
A.4. Interrupt interface
A.5. ICode interface
A.6. DCode interface
A.7. System bus interface
A.8. Private Peripheral Bus interface
A.9. ITM interface
A.10. AHB-AP interface
A.11. ETM interface
A.12. AHB Trace Macrocell interface
A.13. Test interface
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Cortex-M3 block diagram
1.2. Cortex-M3 pipeline stages
2.1. Processor register set
2.2. Application Program Status Registerbit assignments
2.3. Interrupt Program Status Register bit assignments
2.4. Execution Program Status Register
2.5. Little-endian and big-endian memoryformats
4.1. Processor memory map
4.2. Bit-band mapping
5.1. Stack contents after a pre-emption
5.2. Exception entry timing
5.3. Tail-chaining timing
5.4. Late-arriving exception timing
5.5. Exception exit timing
5.6. Interrupt handling flowchart
5.7. Pre-emption flowchart
5.8. Return from interrupt flowchart
6.1. Reset signals
6.2. Power-on reset
6.3. Internal reset synchronization
7.1. SLEEPING power control example
7.2. SLEEPDEEP power control example
8.1. Interrupt Controller Type Registerbit assignments
8.2. SysTick Control and Status Registerbit assignments
8.3. SysTick Reload Value Register bitassignments
8.4. SysTick Current Value Register bitassignments
8.5. SysTick Calibration Value Registerbit assignments
8.6. Interrupt Priority Registers 0-31bit assignments
8.7. CPUID Base Register bit assignments
8.8. Interrupt Control State Registerbit assignments
8.9. Vector Table Offset Register bitassignments
8.10. Application Interrupt and Reset ControlRegister bit assignments
8.11. System Control Register bit assignments
8.12. Configuration Control Register bitassignments
8.13. System Handler Priority Registersbit assignments
8.14. System Handler Control and StateRegister bit assignments
8.15. Configurable Fault Status Registersbit assignments
8.16. Memory Manage Fault Register bitassignments
8.17. Bus Fault Status Register bit assignments
8.18. Usage Fault Status Register bit assignments
8.19. Hard Fault Status Register bit assignments
8.20. Debug Fault Status Register bit assignments
8.21. Software Trigger Interrupt Registerbit assignments
9.1. MPU Type Register bit assignments
9.2. MPU Control Register bit assignments
9.3. MPU Region Number Register bit assignments
9.4. MPU Region Base Address Registerbit assignments
9.5. MPU Region Attribute and Size Registerbit assignments
10.1. Debug Halting Control and StatusRegister format
10.2. Debug Core Register Selector Registerformat
10.3. Debug Exception and Monitor Control Register format
11.1. System debug access block diagram
11.2. Flash Patch Control Register bitassignments
11.3. Flash Patch Remap Register bit assignments
11.4. Flash Patch Comparator Registersbit assignments
11.5. DWT Control Register bit assignments
11.6. DWT CPI Count Register bit assignments
11.7. DWT Exception Overhead Count Registerbit assignments
11.8. DWT Sleep Count Register bit assignments
11.9. DWT LSU Count Register bit assignments
11.10. DWT Fold Count Register bit assignments
11.11. DWT Mask Registers 0-3 bit assignments
11.12. DWT Function Registers 0-3 bit assignments
11.13. ITM Trace Privilege Register bitassignments
11.14. ITM Trace Control Register bit assignments
11.15. ITM Integration Write Register bitassignments
11.16. ITM Integration Read Register bitassignments
11.17. ITM Integration Mode Control bitassignments
11.18. ITM Lock Status Register bit assignments
11.19. AHB-AP Control and Status Word Register
11.20. AHB-AP ID Register
13.1. Block diagram of the TPIU (non-ETMversion)
13.2. Block diagram of the TPIU (ETM version)
13.3. Supported Sync Port Size Registerbit assignments
13.4. Async Clock Prescaler Register bitassignments
13.5. Selected Pin Protocol Register bitassignments
13.6. Formatter and Flush Status Registerbit assignments
13.7. Formatter and Flush Control Registerbit assignments
13.8. Integration Test Register-ITATBCTR2bit assignments
13.9. Integration Test Register-ITATBCTR0bit assignments
13.10. Dedicated pin used for TRACESWO
13.11. SWO shared with TRACEPORT
13.12. SWO shared with JTAG-TDO
14.1. ICode/DCode multiplexer
15.1. ETM block diagram
15.2. Return from exception packet encoding
15.3. Exception encoding for branch packet
16.1. Conditional branch backwards nottaken
16.2. Conditional branch backwards taken
16.3. Conditional branch forwards not taken
16.4. Conditional branch forwards taken
16.5. Unconditional branch without pipelinestalls
16.6. Unconditional branch with pipelinestalls
16.7. Unconditional branch in execute aligned
16.8. Unconditional branch in execute unaligned
16.9. Example of an opcode sequence

List of Tables

1.1. 16-bit Cortex-M3 instruction summary
1.2. 32-bit Cortex-M3 instruction summary
2.1. Application Program Status Register bit assignments
2.2. Interrupt Program Status Register bit assignments
2.3. Bit functions of the EPSR
2.4. Nonsupported Thumb instructions
2.5. Supported Thumb-2 instructions
3.1. NVIC registers
3.2. Core debug registers
3.3. Flash patch register summary
3.4. DWT register summary
3.5. ITM register summary
3.6. AHB-AP register summary
3.7. Summary of Debug interface port registers
3.8. MPU registers
3.9. TPIU registers
3.10. ETM registers
4.1. Memory interfaces
4.2. Memory region permissions
4.3. ROM table
5.1. Exception types
5.2. Priority-based actions of exceptions
5.3. Priority grouping
5.4. Exception entry steps
5.5. Exception exit steps
5.6. Exception return behavior
5.7. Reset actions
5.8. Reset boot-up behavior
5.9. Transferring to exception processing
5.10. Faults
5.11. Debug faults
5.12. Fault status and fault address registers
5.13. Privilege and stack of different activation levels
5.14. Exception transitions
5.15. Exception subtype transitions
6.1. Cortex-M3 processor clocks
6.2. Cortex-M3 macrocell clocks
6.3. Reset inputs
6.4. Reset modes
7.1. Supported sleep modes
8.1. NVIC registers
8.2. Interrupt Controller Type Register bit assignments
8.3. SysTick Control and Status Register bit assignments
8.4. SysTick Reload Value Register bit assignments
8.5. SysTick Current Value Register bit assignments
8.6. SysTick Calibration Value Register bit assignments
8.7. Interrupt Set-Enable Register bit assignments
8.8. Interrupt Clear-Enable Register bit assignments
8.9. Interrupt Set-Pending Register bit assignments
8.10. Interrupt Clear-Pending Registers bit assignments
8.11. Active Bit Register bit assignments
8.12. Interrupt Priority Registers 0-31 bit assignments
8.13. CPUID Base Register bit assignments
8.14. Interrupt Control State Register bit assignments
8.15. Vector Table Offset Register bit assignments
8.16. Application Interrupt and Reset Control Register bit assignments
8.17. System Control Register bit assignments
8.18. Configuration Control Register bit assignments
8.19. System Handler Priority Registers bit assignments
8.20. System Handler Control and State Register bit assignments
8.21. Memory Manage Fault Status Register bit assignments
8.22. Bus Fault Status Register bit assignments
8.23. Usage Fault Status Register bit assignments
8.24. Hard Fault Status Register bit assignments
8.25. Debug Fault Status Register bit assignments
8.26. Memory Manage Fault Address Register bit assignments
8.27. Bus Fault Address Register bit assignments
8.28. Auxiliary Fault Status Register bit assignments
8.29. Software Trigger Interrupt Register bit assignments
9.1. MPU registers
9.2. MPU Type Register bit assignments
9.3. MPU Control Register bit assignments
9.4. MPU Region Number Register bit assignments
9.5. MPU Region Base Address Register bit assignments
9.6. MPU Region Attribute and Size Register bit assignments
9.7. MPU protection region size field
9.8. TEX, C, B encoding
9.9. Cache policy for memory attribute encoding
9.10. AP encoding
9.11. XN encoding
10.1. Core debug registers
10.2. Debug Halting Control and Status Register
10.3. Debug Core Register Selector Register
10.4. Debug Exception and Monitor Control Register
10.5. Application registers for use in core debug
11.1. FPB register summary
11.2. Flash Patch Control Register bit assignments
11.3. COMP mapping
11.4. Flash Patch Remap Register bit assignments
11.5. Flash Patch Comparator Registers bit assignments
11.6. DWT register summary
11.7. DWT Control Register bit assignments
11.8. DWT Current PC Sampler Cycle Count Register bit assignments
11.9. DWT CPI Count Register bit assignments
11.10. DWT Exception Overhead Count Register bit assignments
11.11. DWT Sleep Count Register bit assignments
11.12. DWT LSU Count Register bit assignments
11.13. DWT Fold Count Register bit assignments
11.14. DWT Program Counter Sample Register bit assignments
11.15. DWT Comparator Registers 0-3 bit assignments
11.16. DWT Mask Registers 0-3 bit assignments
11.17. Bit functions of DWT Function Registers 0-3
11.18. Settings for DWT Function Registers
11.19. ITM register summary
11.20. ITM Trace Enable Register bit assignments
11.21. ITM Trace Privilege Register bit assignments
11.22. ITM Trace Control Register bit assignments
11.23. ITM Integration Write Register bit assignments
11.24. ITM Integration Read Register bit assignments
11.25. ITM Integration Mode Control Register bit assignments
11.26. ITM Lock Access Register bit assignments
11.27. ITM Lock Status Register bit assignments
11.28. AHB-AP register summary
11.29. AHB-AP Control and Status Word Register bit assignments
11.30. AHB-AP Transfer Address Register bit assignments
11.31. AHB-AP Data Read/Write Register bit assignments
11.32. AHB-AP Banked Data Register bit assignments
11.33. AHB-AP Debug ROM Address Register bit assignments
11.34. AHB-AP ID Register bit assignments
13.1. Trace out port signals
13.2. ATB port signals
13.3. Miscellaneous configuration inputs
13.4. TPIU registers
13.5. Async Clock Prescaler Register bit assignments
13.6. Selected Pin Protocol Register bit assignments
13.7. Formatter and Flush Status Register bit assignments
13.8. Formatter and Flush Control Register bit assignments
13.9. Integration Test Register-ITATBCTR2 bit assignments
13.10. Integration Test Register-ITATBCTR0 bit assignments
14.1. Instruction fetches
14.2. Bus mapper unaligned accesses
14.3. Memory attributes
14.4. Interface timing characteristics
15.1. ETM core interface inputs and outputs
15.2. Miscellaneous configuration inputs
15.3. Trace port signals
15.4. Other signals
15.5. Clocks and resets
15.6. APB interface signals
15.7. Cortex-M3 resources
15.8. Exception tracing mapping
15.9. ETM registers
16.1. ETM interface ports
16.2. Branch status signal function
16.3. Example of an opcode sequence
17.1. AHB interface ports
18.1. Instruction timings
19.1. Miscellaneous input ports timing parameters
19.2. Interrupt input ports timing parameters
19.3. AHB input ports timing parameters
19.4. PPB input port timing parameters
19.5. Debug input ports timing parameters
19.6. Test input ports timing parameters
19.7. ETM input port timing parameters
19.8. Miscellaneous output ports timing parameters
19.9. AHB output ports timing parameters
19.10. PPB output ports timing parameters
19.11. Debug interface output ports timing parameters
19.12. ETM interface output ports timing parameters
19.13. HTM interface output ports timing parameters
19.14. Test output ports timing parameters
A.1. Clock signals
A.2. Reset signals
A.3. Miscellaneous signals
A.4. Interrupt interface
A.5. ICode interface
A.6. DCode interface
A.7. System bus interface
A.8. Private Peripheral Bus interface
A.9. ITM interface
A.10. AHB-AP interface
A.11. ETM interface
A.12. HTM interface
A.13. Test interface

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

ConfidentialityStatus

This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

Product Status

The information in this document is Final (information ona developed product).

Revision History
Revision A 15December 2005 First Release
Revision B 13January 2006 Confidentiality status amended
Revision C 10May 2006 First Release for r1p0
Revision D 27September 2006 First Release for r1p1
Revision E 13June 2007 Minor update with no technical changes
Copyright © 2005, 2006 ARM Limited. All rights reserved. ARM DDI 0337E
Non-Confidential