Cortex-M3 Technical Reference Manual: 11.3. TPIU programmers model

11.3. TPIU programmers model

Table 11.1 provides a summary of the TPIU registers. Depending on the implementation of your processor, the TPIU registers might not be present, or the CoreSight TPIU might be present instead. Any register that is configured as not present reads as zero.

Table 11.1. TPIU registers

Address	Name	Type	Reset	Description
`0xE0040000`	TPIU_SSPSR	RO	`0x0xx`	Supported Parallel Port Size Register
`0xE0040004`	TPIU_CSPSR	RW	`0x01`	Current Parallel Port Size Register
`0xE0040010`	TPIU_ACPR	RW	`0x0000`	Asynchronous Clock Prescaler Register, TPIU_ACPR
`0xE00400F0`	TPIU_SPPR	RW	`0x01`	Selected Pin Protocol Register
`0xE0040300`	TPIU_FFSR	RO	`0x08`	Formatter and Flush Status Register, TPIU_FFSR
`0xE0040304`	TPIU_FFCR	RW	`0x102`	Formatter and Flush Control Register, TPIU_FFCR
`0xE0040308`	TPIU_FSCR	RO	`0x00`	Formatter Synchronization Counter Register
`0xE0040EE8`	TRIGGER	RO	`0x0`	TRIGGER
`0xE0040EEC`	FIFO data 0	RO	`0x--000000`	Integration FIFO 0 Data
`0xE0040EF0`	ITATBCTR2	RO	`0x0`	ITATBCTR2
`0xE0040EFC`	FIFO data 1	RO	`0x--000000`	Integration FIFO 1 Data
`0xE0040EF8`	ITATBCTR0	RO	`0x0`	ITATBCTR0
`0xE0040F00`	ITCTRL	RW	`0x0`	Integration Mode Control, TPIU_ITCTRL
`0xE0040FA0`	CLAIMSET	RW	`0xF`	Claim tag set
`0xE0040FA4`	CLAIMCLR	RW	`0x0`	Claim tag clear
`0xE0040FC8`	DEVID	RO	-	TPIU_DEVID
`0xE0040FD0`	PID4	RO	`0x04`	Peripheral identification registers
`0xE0040FD4`	PID5	RO	`0x00`
`0xE0040FD8`	PID6	RO	`0x00`
`0xE0040FDC`	PID7	RO	`0x00`
`0xE0040FE0`	PID0	RO	`0xA1`
`0xE0040FE4`	PID1	RO	`0xB9`
`0xE0040FE8`	PID2	RO	`0x0B`
`0xE0040FEC`	PID3	RO	`0x00`
`0xE0040FF0`	CID0	RO	`0x0D`	Component identification registers
`0xE0040FF4`	CID1	RO	`0x90`
`0xE0040FF8`	CID2	RO	`0x05`
`0xE0040FFC`	CID3	RO	`0xB1`

The following sections describe the TPIU registers whose implementation is specific to this processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in the CoreSight Components Technical Reference Manual. Other registers are described in the ARMv7-M Architecture Reference Manual.

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